Castellated superjunction transistors

Patent metadata

Field	Value
Publication number	US-2020373384-A1
Application number	US-202016992244-A
Country	US
Kind code	A1
Filing date	Aug 13, 2020
Priority date	Jan 21, 2019
Publication date	Nov 26, 2020
Grant date	—

Abstract

A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

First claim

What is claimed is:

1 . A method of forming a transistor, the method comprising:
etching openings in a superlattice structure comprising a plurality of heterostructures over a base structure to form a plurality of multichannel gate ridges spaced apart from one another by gate-controlled non-channel trench openings, each of the plurality of multichannel gate ridges being formed from the plurality of heterostructures and each having sidewalls, a plurality of multichannel drain ridges spaced apart from one another by drain-side non-channel trench openings, each of the plurality of multichannel drain ridges being formed from the plurality of heterostructures and each having sidewalls, and a gate interface formed from the plurality of heterostructures that runs transverse to the plurality of multichannel gate ridges and multichannel drain ridges and separates the drain-side non-channel trench openings from the gate-controlled non-channel trench opening; filling the drain-side non-channel trench openings with a doped semiconducting material; and forming a gate contact that wraps around and substantially surrounds the top and sides of each the plurality of multichannel ridges along at least a portion of its depth, filling the gate-controlled non-channel trench openings.

2 . The method of claim 1 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the AlGaN layer is doped.

3 . The method of claim 1 , wherein the doped semiconducting material is boron doped diamond.

4 . The method of claim 1 , wherein the doped semiconducting material is Mg- or Ca-doped GaN.

5 . The method of claim 1 , wherein etching openings in a superlattice structure comprises forming an etch mask over the superlattice structure to provide respective areas for forming the gate-controlled non-channel trench openings and the drain-side non-channel trench openings.

6 . The method of claim 5 , wherein the etching of the openings in the superlattice structure forms the gate-controlled non-channel trench openings in a gate region and the drain-side non-channel trench openings in a superjunction region.

7 . The method of claim 6 , wherein the gate interface connects the gate region and the superconducting region.

8 . The method of claim 6 , wherein forming an etch mask over the superlattice structure comprises employing the etching mask to form the plurality of multichannel drain ridges, the plurality of multichannel gate ridges and the gate-controlled and the drain-side non-channel trench openings.

9 . The method of claim 6 , wherein the etch mask is a first etch mask, and the method further comprises forming a second etch mask to form patterned openings over respective portions of the superlattice structure.

10 . The method of claim 9 , wherein the doped semiconducting material is a first doped semiconducting material, and the method further comprises:
etching the respective portions of the superlattice structure to form source and drain openings; and filling the source and drain openings with a second doped semiconducting material to form source and drain regions.

11 . The method of claim 10 , wherein the second doped semiconducting material is doped Gallium Nitride.

12 . The method of claim 10 , wherein the source region is connected via a source interface to source-side non-channel trench openings and the drain region is connected via a drain interface to the drain-side non-channel trench openings.

13 . The method of claim 10 , wherein the drain-side non-channel trench openings are filled with the first doped semiconducting material in response to filling the source and the drain openings with the second doped semiconducting material.

14 . The method of claim 13 , wherein the first doped semiconducting material is a boron doped diamond or is Mg- or Ca-doped GaN.

15 . The method of claim 14 , wherein forming the gate contact comprises forming a castellated gate contact over the plurality of multichannel drain ridges and through source-side non-channel openings in the gate region.

16 . The method of claim 15 , further comprising forming the superlattice structure comprising the plurality of heterostructures over the base structure.

17 . The method of claim 1 , further comprising:
etching a source opening on a source side of the plurality of multichannel gate ridges and a drain opening on the drain-side of the plurality of multichannel ridges; and filling the source opening and drain opening with a doped material to form a drain region and a source region.

18 . The method of claim 17 , further comprising forming a source contact disposed over the source region and a drain contact disposed over the drain region.

19 . The method of claim 18 , wherein forming the gate contact comprises forming a castellated gate contact over the plurality of multichannel drain ridges and through the source-side non-channel openings in a gate region.

20 . The method of claim 19 , wherein the doped semiconducting material is a boron doped diamond or is Mg- or Ca-doped GaN.

Assignees

• Chang Josephine Bea
• Stewart Eric J
• Nagamatsu Ken Alfred
• Howell Robert S
• Gupta Shalini
• Northrop Grumman Systems Corp

Inventors

• Chang Josephine Bea
• Stewart Eric J
• Nagamatsu Ken Alfred
• Howell Robert S
• Gupta Shalini

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3406

  Carbon, e.g. diamond-like carbon · CPC title

• H10W74/481

  comprising semiconductor materials · CPC title