Timed Data Transfer between a Host System and a Memory Sub-System

Patent metadata

Field	Value
Publication number	US-2020356484-A1
Application number	US-202016865244-A
Country	US
Kind code	A1
Filing date	May 1, 2020
Priority date	May 6, 2019
Publication date	Nov 12, 2020
Grant date	—

Abstract

A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.

First claim

What is claimed is:

1 . A method, comprising:
receiving, in a memory sub-system, a plurality of streams of write commands from a host system; identifying a plurality of media units in the memory sub-system, wherein the plurality of media units are identified to be available to write data from the plurality of streams concurrently; selecting first commands from the plurality of streams for concurrent execution in the plurality of media units; initiating, by the memory sub-system and in response to the first commands from a plurality of write streams being selected for concurrent execution in the plurality of media units, communication of first data of the first commands from the plurality of write streams from the host system to a local buffer memory of the memory sub-system; and executing the first commands concurrently by storing the first data into the a plurality of memory units.

2 . The method of claim 1 , further comprising:
allocating a buffer space for the first data in response to the plurality of media units being available to perform write operations to store the first data; transferring the first data to the plurality of media units; and releasing the buffer space from buffering the first data in response to completion of the transferring the first data to the plurality of media units.

3 . The method of claim 2 , wherein the memory sub-system buffers, in the local buffer memory, no more than a predetermined number of units of data; the predetermined number corresponds to a number of media units in the memory sub-system that are capable of operating independent from each other in writing data; and each unit of data is no more than a maximum amount of data to be written in a media unit in response to a single write command; and the method further comprises:
queuing write commands more than the predetermined number in at least one command queue configured in the local memory of the memory sub-system.

4 . The method of claim 3 , wherein at least a portion of the first commands is selected for execution out of an order according to which commands in the command queue are received.

5 . The method of claim 4 , wherein each respective stream in the plurality of streams being configured to write data sequentially in a logical address space; and the logical address space is defined in a namespace of the memory sub-system.

6 . The method of claim 5 , wherein the namespace is configured with a plurality of zones; and the each respective stream is configured to write in one of the plurality of zones.

7 . The method of claim 6 , wherein each respective zone in the namespace prohibits non-sequential write operations in the logical address space.

8 . The method of claim 7 , wherein the each respective zone in the namespace allows random read operations in the logical address space.

9 . The method of claim 6 , wherein each of the plurality of media units is identified based on being on a separate integrated circuit die of memory units.

10 . A memory sub-system, comprising:
a plurality of media units capable of writing data concurrently; a local buffer memory; and at least one processing device configured to:
receive a plurality of streams of write commands from a host system;
identify one or more first media units among the plurality of media units, wherein the one or more first media units are identified to be available to write data from the plurality of streams concurrently with one or more second media units among the plurality of media units, wherein the one or more second media units are in progress of writing data;
select one or more first commands from the plurality of streams for concurrent execution with one or more second commands that are in progress in the one or more second media units;
initiate, in response to one or more first commands being selected for concurrent execution, communication of first data of the first commands from the plurality of streams from the host system to the local buffer memory of the memory sub-system; and
execute the one or more first commands by storing the first data into the one or more first memory units, concurrently with the one or more second commands in progress in the one or more second media units.

11 . The memory sub-system of claim 10 , wherein each respective stream in the plurality of streams being configured to write data sequentially in a logical address space; the logical address space is defined in a namespace of the memory sub-system; the namespace is configured with a plurality of zones; the each respective stream is configured to write in one of the plurality of zones; each respective zone in the namespace prohibits non-sequential write operations in the logical address space but allows random read operations in the logical address space.

12 . The memory sub-system of claim 11 , wherein each of the plurality of media units is identified based on being on a separate integrated circuit die of memory units.

13 . The memory sub-system of claim 12 , wherein the local buffer memory is static random access memory (SRAM).

14 . The memory sub-system of claim 13 , wherein the memory sub-system has no dynamic random-access memory (DRAM); and the memory sub-system further comprises:
a power-fail hold-up circuit configured to power the static random access memory (SRAM) in a power failure event until content in the static random access memory (SRAM) is stored into the plurality of media units.

15 . The memory sub-system of claim 14 , wherein a capacity of the static random access memory (SRAM) to buffer data of write commands is less than a capacity to buffer all of write commands queued in the memory sub-system.

16 . A non-transitory computer storage medium storing instructions which, when executed in a memory sub-system, causes the memory sub-system to perform a method, the method comprising:
receiving, in the memory sub-system, a plurality of streams of write commands from a host system; identifying a plurality of media units in the memory sub-system, wherein the plurality of media units are identified to be available to write data from the plurality of streams concurrently; selecting first commands from the plurality of streams for concurrent execution in the plurality of media units; initiating, by the memory sub-system and in response to the first commands from the plurality of streams being selected for concurrent execution in the plurality of media units, communication of first data of the first commands from the host system to a local buffer memory of the memory sub-system; and executing the first commands concurrently by storing the first data into the plurality of memory units.

17 . The non-transitory computer storage medium of claim 16 , wherein the memory sub-system buffers, in the local buffer memory, no more than a predetermined number of units of data; the predetermined number corresponds to a number of media units in the memory sub-system that are capable of operating independent from each other in writing data; and each unit of data is no more than a maximum amount of data to be written in a media unit in response to a single write command.

18 . The non-transitory computer storage medium of claim 17 , wherein, each respective stream in the plurality of streams being configured to write data sequentially in a logical address space; the logical address space is defined in a namespace of the memory sub-system; the namespace is configured with a plurality of zones; the each respective stream is configured to write in one of the plurality of z

Assignees

• Micron Technology Inc

Inventors

• Subbarao Sanjay

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title