Deposition system with integrated carrier cleaning modules

Patent metadata

Field	Value
Publication number	US-2020354828-A1
Application number	US-202016870110-A
Country	US
Kind code	A1
Filing date	May 8, 2020
Priority date	May 10, 2019
Publication date	Nov 12, 2020
Grant date	—

Abstract

A chemical vapor deposition system for semiconductor wafer production is disclosed. The system includes a process cluster coupled to a first end of a transfer chamber. The process cluster is maintained at a pressure that is lower than atmospheric pressure. The process cluster is also configured to apply epitaxial layers on one or more wafers loaded onto a wafer carrier. The system also includes an automatic factory interface coupled to a second end of the transfer chamber. The automatic factory interface is maintained at atmospheric pressure. The system includes one or more wafer carrier cleaning modules coupled to the automatic factory interface and configured to clean one or more of the wafer carriers without removing the wafer carriers from the chemical vapor deposition system.

First claim

1 . A chemical vapor deposition system for semiconductor wafer production, the system comprising:
a transfer chamber having a first end and a second end; an automatic factory interface operably coupled to the first end of the transfer chamber, the automatic factory interface chamber configured to load and unload one or more wafers from one or more wafer carriers; one or more wafer carrier cleaning modules directly coupled to the automatic factory interface, the one or more wafer cleaning modules configured to automatically clean the one or more of the wafer carriers, the one or more wafer carrier cleaning modules further including one or more surface characterization tools to detect one or more surface characteristics of the one or more wafer carriers; and a process cluster operably coupled to the second end of the transfer chamber, the process cluster comprising one or more processing modules.

2 . The chemical vapor deposition system of claim 1 , wherein the one or more wafer carrier cleaning modules further include a wafer carrier cleaning robot.

3 . The chemical vapor deposition system of claim 1 , wherein the process cluster includes a process cluster robot configured to manipulate the wafer carrier into and out of the transfer chamber.

4 . The chemical vapor deposition system of claim 1 , wherein the system includes two or more wafer carrier cleaning modules.

5 . The chemical vapor deposition system of claim 1 , wherein the automatic factory interface robot is configured to manipulate the wafer carrier directly into and out of the wafer carrier cleaning modules.

6 . The chemical vapor deposition system of claim 1 , wherein the one or more wafer carrier cleaning modules further includes one or more storage areas for wafer carriers.

7 . The chemical vapor deposition system of claim 6 , wherein one or more of the storage areas further includes a cooling station.

8 . A wafer carrier cleaning system comprising:
a chamber; a support for supporting a wafer carrier mounted within the chamber; one or more gas injectors mounted within the chamber for injecting one or more cleaning gases; a heater; and one or more surface characterization tools to detect one or more surface characteristics of the wafer carrier.

9 . The wafer carrier cleaning system of claim 8 , wherein the chamber includes exhaust dilution apertures, the exhaust dilution apertures configured for routing the gases out of the chamber.

10 . The wafer carrier cleaning system of claim 8 , wherein the chamber is heated using an array of radio frequency heating coils.

11 . The wafer carrier cleaning system of claim 8 , wherein the chamber is heated by passing electrical current from one or more first electrodes electrically coupled to a first portion of the chamber, through a heating portion of the chamber and then through one or more second electrodes electrically coupled to a second portion of the chamber.

12 . The wafer carrier cleaning system of claim 11 , wherein one or more first electrodes are coupled to a first electrically conducting spacer, the first electrically conducting spacer being coupled to the first portion of the chamber and the one or more second electrodes are coupled to a second electrically conducting spacer, the second electrically conducting spacer being coupled to the second portion of the chamber.

13 . The wafer carrier cleaning system of claim 8 , wherein the chamber is heated using a radiant heat shield array.

14 . The wafer carrier cleaning system of claim 8 , wherein the chamber is heated using an array of radio frequency heating coils arranged outside of the chamber and by passing electrical current from one or more first electrodes electrically coupled to a first portion of the chamber, through a heating portion of the chamber and then through one or more second electrodes electrically coupled to a second portion of the chamber.

15 . The wafer carrier cleaning system of claim 8 , wherein the one or more gas injectors comprise an inlet block configured to inject a purge gas into the chamber and inject a cleaning reactant gas into the chamber.

16 . The wafer carrier cleaning system of claim 8 , wherein the chamber further includes one or more storage areas for wafer carriers.

17 . A method of cleaning wafer carriers comprising:
loading a wafer carrier in need of cleaning into a cleaning chamber; injecting one or more cleaning gases into the cleaning chamber; activating the one or more cleaning gases at a temperature ranging from about 400° C. to about 1000° C. under a pressure ranging from about 100 Torr to about 760 Torr; exposing surfaces of the wafer carrier to the activated one or more cleaning gases; and inspecting the wafer carrier surfaces using one or more surface characterization tools to determine if the wafer carrier has been cleaned.

18 . The method of claim 17 , wherein the surface characterization tools used for inspecting the wafer carrier surfaces include one or more of: a wafer carrier cleaning quality analysis, a wafer carrier cleaning uniformity analysis, and a wafer carrier integrity analysis.

Assignees

• Veeco Instr Inc

Inventors

• Gurary Alexander I
• Deshpande Mandar
• Paranjpe Ajit

Classifications

• H10P72/0462

  characterised by the construction of the processing chambers, e.g. modular processing chambers · CPC title

• H10P72/0434

  mainly by convection · CPC title

• H10P72/0452

  characterised by the layout of the process chambers · CPC title

• H10P72/0436

  mainly by radiation · CPC title

• H10P72/0406

  for cleaning followed by drying, rinsing, stripping, blasting or the like · CPC title