Thin film transistor, manufacturing method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-2020335631-A1
Application number	US-201816309786-A
Country	US
Kind code	A1
Filing date	Apr 4, 2018
Priority date	Jun 27, 2017
Publication date	Oct 22, 2020
Grant date	—

Abstract

A thin film transistor, a manufacturing method thereof, an array substrate, and a display device are provided. The thin film transistor comprises a base substrate, a gate on the base substrate, a gate insulating layer covering the gate, an active layer on the gate insulating layer, a first electrode and a second electrode over and electrically connected to the active layer, and a first insulating portion between the gate insulating layer and the first electrode. An orthographic projection of the first insulating portion on the base substrate, an orthographic projection of the first electrode on the base substrate, and an orthographic projection of a boundary between a side surface of the gate and an upper surface of the gate on the base substrate at least partially overlap.

First claim

1 . A thin film transistor comprising:
a base substrate, a gate on the base substrate, a gate insulating layer covering on the gate, an active layer on the gate insulating layer, a first electrode and a second electrode over on the active layer and electrically connected to the active layer, and a first insulating portion between the gate insulating layer and the first electrode, wherein an orthographic projection of the first insulating portion on the base substrate, an orthographic projection of the first electrode on the base substrate, and an orthographic projection of a boundary between a side surface of the gate and an upper surface of the gate on the base substrate at least partially overlap one another.

2 . The thin film transistor according to claim 1 ,
wherein the active layer comprises a first groove, and wherein the first insulating portion fills the first groove.

3 . The thin film transistor according to claim 1 , wherein the first insulating portion is between the first electrode and the active layer.

4 . The thin film transistor according to claim 1 , further comprising:
a second insulating portion between the gate insulating layer and the second electrode, wherein an orthographic projection of the second insulating portion on the base substrate, an orthographic projection of the second electrode on the base substrate, and the orthographic projection of the boundary between the side surface of the gate and the upper surface of the gate on the base substrate at least partially overlap one another.

5 . The thin film transistor according to claim 4 , wherein the active layer comprises a second groove, and the second insulating portion fills the second groove.

6 . The thin film transistor according to claim 4 , wherein the second insulating portion is between the second electrode and the active layer.

7 . The thin film transistor according to claim 2 , wherein the first groove comprises a through hole penetrating the active layer.

8 . The thin film transistor according to claim 5 , wherein the second groove comprises a through hole penetrating the active layer.

9 . The thin film transistor according to claim 1 , wherein the first insulating portion is located between the active layer and the gate insulating layer.

10 . The thin film transistor according to claim 4 , wherein the second insulating portion is located between the active layer and the gate insulating layer.

11 . The thin film transistor according to claim 1 , further comprising:
an etch barrier layer over the active layer and between the first electrode and the second electrode.

12 . The thin film transistor according to claim 11 , wherein a material of the first insulating portion comprises a same material as that of the etch barrier layer.

13 . The thin film transistor according to claim 11 , wherein the thin film transistor comprises a second insulating portion, a material of the second insulating portion is a same material as that of the etch barrier layer.

14 . An array substrate comprising the thin film transistor according to claim 1 .

15 . (canceled)

16 . A manufacturing method of a thin film transistor, comprising:
forming a pattern of a gate on a base substrate; forming a gate insulating layer on the gate; forming a pattern of an active layer on the gate insulating layer; forming, on the active layer, patterns of a first electrode and a second electrode electrically connected to the active layer, wherein, after forming the gate insulating layer and before forming the patterns of the first electrode and the second electrode, the manufacturing method further comprises forming a pattern of a first insulating portion, and wherein an orthographic projection of the first insulating portion on the base substrate, an orthographic projection of the first electrode on the base substrate, and an orthographic projection of a boundary between a side surface of the gate and an upper surface of the gate on the base substrate at least partially overlap one another.

17 . The manufacturing method according to claim 16 , wherein after forming the pattern of the active layer and before forming the patterns of the first electrode and the second electrode, the manufacturing method further comprises forming a pattern of a second insulating portion, and
wherein an orthographic projection of the second insulating portion on the base substrate, an orthographic projection of the second electrode on the base substrate, and the orthographic projection of the boundary between the side surface of the gate and the upper surface of the gate on the base substrate at least partially overlap one another.

18 . The manufacturing method according to claim 17 , wherein after forming the pattern of the active layer and before forming the patterns of the first electrode and the second electrode, the manufacturing method further comprises:
forming a pattern of an etch barrier layer.

19 . The manufacturing method according to claim 18 , wherein said forming the pattern of the first insulating portion and the pattern of the second insulating portion comprises:
forming a first groove and a second groove in the active layer; forming the pattern of the first insulating portion in the first groove while forming the pattern of the etch barrier layer; and forming the pattern of the second insulating portion in the second groove while forming the pattern of the etch barrier layer.

20 . The manufacturing method according to claim 18 , wherein the first insulating portion, the second insulating portion, and the etch barrier layer are formed by a same patterning process.

21 . The manufacturing method according to claim 16 , wherein, after forming the patterns of the first electrode and the second electrode, the manufacturing method further comprises:
forming a passivation layer on the first electrode and the second electrode.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Park Kuhyun

Classifications

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6704 Primary

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/6713 Primary

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title