Semiconductor devices

Patent metadata

Field	Value
Publication number	US-2020335520-A1
Application number	US-202016921185-A
Country	US
Kind code	A1
Filing date	Jul 6, 2020
Priority date	Jul 25, 2017
Publication date	Oct 22, 2020
Grant date	—

Abstract

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a stack structure comprising conductive layers stacked on the substrate; and a dummy structure penetrating a stepped region of the stack structure, wherein a portion of the dummy structure comprises:
a first segment extending in a first direction in a plane parallel to an upper surface of the substrate; and
a second segment protruding from the first segment in a second direction, in the plane, that intersects the first direction.

2 . The semiconductor device of claim 1 , wherein the portion of the dummy structure comprises an L shape.

3 . The semiconductor device of claim 1 ,
wherein the portion of the dummy structure comprises an upper portion of the dummy structure, wherein the plane comprises a first plane, wherein a lower portion of the dummy structure comprises a first shape in a second plane that is parallel to the first plane and is between the first plane and the substrate, and wherein the first shape is different from a second shape of the upper portion of the dummy structure in the first plane.

4 . The semiconductor device of claim 1 ,
wherein the portion of the dummy structure comprises an upper portion of the dummy structure, wherein the plane comprises a first plane, and wherein a lower portion of the dummy structure extends in a third direction, intersecting the first direction and the second direction, in a second plane that is parallel to the first plane and is between the first plane and the substrate.

5 . The semiconductor device of claim 4 , wherein the lower portion of the dummy structure comprises:
an elliptical shape, in the second plane, comprising a primary axis that extends in the third direction; or a bar shape, in the second plane, extending in the third direction.

6 . The semiconductor device of claim 1 , wherein the portion of the dummy structure comprises a concave segment at a location where the first segment and the second segment are connected to each other.

7 . The semiconductor device of claim 1 , wherein a lowermost surface of the dummy structure is in contact with the substrate.

8 . The semiconductor device of claim 1 ,
wherein the substrate comprises a cell array region and a connection region, wherein the dummy structure comprises a support structure on the connection region, wherein the semiconductor device further comprises a vertical structure on the cell array region and penetrating the stack structure, and wherein a first shape of the first segment and the second segment in the plane comprises a different shape from, and a larger size than, a second shape of the vertical structure in the plane.

9 . A semiconductor device comprising:
a substrate comprising a cell array region and a connection region; a stack structure comprising a plurality of conductive layers stacked on the substrate, a first one of the plurality of conductive layers comprising a pad region that protrudes relative to an overlying second one of the plurality of conductive layers on the connection region; a vertical structure on the cell array region and penetrating a vertical memory region of the stack structure; and a support structure penetrating the pad region, wherein, in a horizontal cross section, a portion of the support structure comprises an inwardly-curved segment.

10 . The semiconductor device of claim 9 , further comprising a contact plug electrically connected to the pad region.

11 . The semiconductor device of claim 10 , wherein the inwardly-curved segment faces the contact plug.

12 . The semiconductor device of claim 9 ,
wherein the portion of the support structure comprises:
a first segment extending in a first direction in the horizontal cross section; and
a second segment protruding from the first segment in a second direction in the horizontal cross section, the second direction intersecting the first direction, and
wherein the inwardly-curved segment is at a location where the first segment and the second segment are connected to each other.

13 . The semiconductor device of claim 12 ,
wherein the portion of the support structure comprises an upper portion of a dummy structure, wherein a lower portion of the dummy structure extends in a third direction intersecting the first direction and the second direction.

14 . The semiconductor device of claim 9 , wherein a lowermost surface of the support structure is in contact with the substrate.

15 . A semiconductor device comprising:
a substrate comprising a cell array region and a connection region; a stack structure comprising conductive layers stacked on the substrate, the conductive layers comprising a stepped structure on the connection region; and a support structure on the connection region and penetrating the stepped structure, wherein the support structure comprises:
a dummy lower semiconductor pattern on the substrate; and
a dummy conductive pad on the dummy lower semiconductor pattern,
wherein, in a horizontal cross-sectional view, the dummy conductive pad comprises:
a first segment extending in a first direction; and
a second segment protruding in a second direction from the first segment, the second direction crossing the first direction.

16 . The semiconductor device of claim 15 , wherein, in the horizontal cross-sectional view, the dummy conductive pad comprises a non-circular and non-elliptical shape.

17 . The semiconductor device of claim 15 ,
wherein the horizontal cross-sectional view comprises a first horizontal cross-sectional view, and wherein, in a second horizontal cross-sectional view, the dummy lower semiconductor pattern extends in a third direction crossing the first direction and the second direction.

18 . The semiconductor device of claim 17 , wherein, in the second horizontal cross sectional view, the dummy lower semiconductor pattern comprises an elliptical shape comprising a major axis that extends in the third direction or a bar shape extending in the third direction.

19 . The semiconductor device of claim 15 , wherein the support structure further comprises a dummy upper semiconductor pattern between the dummy lower semiconductor pattern and the dummy conductive pad.

20 . The semiconductor device of claim 15 , further comprising a vertical structure on the cell array region and penetrating the stack structure,
wherein the vertical structure comprises:
a lower semiconductor pattern on the substrate;
a conductive pad on the lower semiconductor pattern; and
an upper semiconductor pattern between the lower semiconductor pattern and the conductive pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Kwangyoung
• Kim Jongwon
• Eun Dongseog
• Lee Joonhee

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title