Semiconductor substrate with integrated inductive component

Patent metadata

Field	Value
Publication number	US-2020321430-A1
Application number	US-202016905197-A
Country	US
Kind code	A1
Filing date	Jun 18, 2020
Priority date	May 11, 2016
Publication date	Oct 8, 2020
Grant date	—

Abstract

In an integrated circuit (IC), a semiconductor substrate has a first side and an opposite second side. The second side has a trench. Circuitry is on the first side. An inductive structure is within the trench. The inductive structure is connected to the circuitry through vias in the semiconductor substrate. The semiconductor substrate is mounted on a package substrate. At least a portion of the inductive structure contacts the package substrate. The circuitry is coupled to the inductive structure through wires to the package substrate.

First claim

What is claimed is:

1 . An integrated circuit (IC) comprising:
a semiconductor substrate having a first side and an opposite second side, the second side having a trench; circuitry on the first side; an inductive structure within the trench, the inductive structure connected to the circuitry through vias in the semiconductor substrate; and a package substrate on which the semiconductor substrate is mounted, in which at least a portion of the inductive structure contacts the package substrate, and the circuitry is coupled to the inductive structure through wires to the package substrate.

2 . The IC of claim 1 , wherein the inductive structure is a first inductive structure, and the IC further comprises a second inductive structure within the semiconductor substrate, the second inductive structure configured to inductively couple with the first inductive structure.

3 . The IC of claim 2 , wherein: the semiconductor substrate includes an insulating layer and first and second substrate layers; the first and second substrate layers are separated by the insulating layer; the first inductive structure is within the first substrate layer; and the second inductive structure is within the second substrate layer.

4 . The IC of claim 1 , wherein the trench has a depth in a range of 25-500 um.

5 . The IC of claim 1 , wherein the trench is at least four times as deep as it is wide.

6 . The IC of claim 1 , wherein the semiconductor substrate is a silicon-on-insulator substrate, and the trench is within an insulator portion of the semiconductor substrate.

7 . The IC of claim 1 , wherein the package substrate is a lead frame.

8 . A system comprising:
a system substrate; an integrated circuit (IC) mounted on the system substrate, the IC including: a semiconductor substrate having a first side and an opposite second side, the second side having a trench; circuitry on the first side; and an inductive structure within the trench; and a package substrate, the inductive structure coupled to the circuitry via the package substrate.

9 . The system of claim 8 , wherein the inductive structure is a first inductive structure, and the IC further comprises a second inductive structure within the semiconductor substrate, the second inductive structure configured to inductively couple with the first inductive structure.

10 . The system of claim 9 , wherein: the semiconductor substrate includes an insulating layer and first and second substrate layers; the first and second substrate layers are separated by the insulating layer; the first inductive structure is within the first substrate layer; and the second inductive structure is within the second substrate layer.

11 . The system of claim 8 , wherein the trench has a depth in a range of 25-500 um.

12 . The system of claim 8 , wherein the trench is at least four times as deep as it is wide.

13 . The system of claim 8 , wherein the semiconductor substrate is a silicon-on-insulator substrate, and the trench is within an insulator portion of the semiconductor substrate.

14 . The system of claim 8 , wherein the package substrate is a lead frame.

15 . A method of making an integrated circuit, the method comprising:
fabricating circuitry on a first side of a semiconductor substrate of the integrated circuit; etching a trench into a second side of the semiconductor substrate; filling the trench with an electrically conductive material to form a coil structure; coupling the coil structure to the circuitry through vias in the semiconductor substrate; mounting the semiconductor substrate on a package substrate, so at least a portion of the coil structure contacts the package substrate; and coupling the circuitry to the coil structure by coupling the circuitry through wires to the package substrate.

16 . The method of claim 15 , wherein the coil structure includes first and second coils, and the second coil is configured to inductively couple with the first coil.

17 . The method of claim 16 , wherein: the semiconductor substrate includes an insulating layer and first and second substrate layers; the first and second substrate layers are separated by the insulating layer; the first coil is within the first substrate layer; the second coil is within the second substrate layer; and the method further comprises:
coupling the circuitry to the second coil.

18 . The method of claim 15 , wherein etching the trench includes etching the trench to a depth in a range of 25-500 um.

19 . The method of claim 15 , wherein etching the trench includes etching the trench to be at least four times as deep as it is wide.

20 . The method of claim 15 , wherein the semiconductor substrate is a silicon-on-insulator substrate, and etching the trench includes etching the trench in an insulator portion of the semiconductor substrate.

21 . The method of claim 15 , wherein the package substrate is a lead frame.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Massolini Roberto Giampiero
• Carothers Daniel

Classifications

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title