Vertical semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2020295028-A1
Application number	US-201916570089-A
Country	US
Kind code	A1
Filing date	Sep 13, 2019
Priority date	Mar 15, 2019
Publication date	Sep 17, 2020
Grant date	—

Abstract

A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

First claim

What is claimed is:

1 . A method for fabricating a vertical semiconductor device, comprising:
forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate; and forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein the forming of the asymmetric stepped trench includes:
forming a first stepped sidewall that is defined at an edge of the pad stack; and
forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

2 . The method of claim 1 , wherein the second stepped sidewall is formed to have a steeper tilt than the first stepped sidewall.

3 . The method of claim 1 , wherein the first stepped sidewall includes a plurality of first steps, and the second stepped sidewall includes a plurality of second steps, and
the second steps are formed to have a greater height than the first steps.

4 . The method of claim 1 , wherein the first stepped sidewall and the second stepped sidewall have the same height.

5 . The method of claim 4 , wherein the first stepped sidewall includes a plurality of first steps, and the second stepped sidewall includes a plurality of second steps, and
the number of the second steps is smaller than the number of the first steps.

6 . The method of claim 5 , wherein each of the first steps and the second steps includes a dielectric layer and sacrificial layer stack where a dielectric layer and a sacrificial layer are stacked, and
the first steps include a stack of a pair of a dielectric layer and a sacrificial layer, and the second steps include a stack of at least two pairs of a dielectric layer and a sacrificial layer.

7 . The method of claim 1 , further comprising:
forming an inter-layer dielectric layer filling the vertical trench and the asymmetric stepped trench, after the forming of the asymmetric stepped trench; planarizing the inter-layer dielectric layer to expose upper surfaces of the dummy stacks; replacing each of sacrificial layers of the dummy stacks, the pad stack, and the dummy pad stack with a conductive layer; and forming contact plugs that are coupled to the conductive layers of the pad stack by penetrating through the inter-layer dielectric layer.

8 . The method of claim 1 , wherein the forming of the vertical trench that divides the upper multi-layered stack into the dummy stacks, and the forming of the asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into the pad stack and the dummy pad stack includes:
forming a symmetric stepped trench by etching the upper multi-layered stack; patterning the symmetric stepped trench into an initial asymmetric stepped trench; forming a mask including an opening that exposes the initial asymmetric stepped trench; and etching the initial asymmetric stepped trench and the lower multi-layered stack to form the asymmetric stepped trench in the lower multi-layered stack.

9 . The method of claim 8 , wherein the asymmetric stepped trench has the same shape as a shape of the initial asymmetric stepped trench.

10 . The method of claim 8 , wherein the initial asymmetric stepped trench and the lower multi-layered stack are etched by an etch-back process using the mask as an etch barrier, and
the initial asymmetric stepped trench is etched and patterned into the vertical trench during the etch-back process.

11 . The method of claim 8 , wherein in the forming of the mask including the opening that exposes the initial asymmetric stepped trench, the opening includes:
a first sidewall that exposes one side of an uppermost step of the initial stepped trench through a first width, and a second sidewall that exposes another side of the uppermost step of the initial stepped trench through a second width, which is smaller than the first width.

12 . The method of claim 8 , wherein the forming of the symmetric stepped trench by etching the upper multi-layered stack includes:
repeatedly performing an etch process of the upper multi-layered stack using a first slim mask, and a slimming process of the first slim mask.

13 . The method of claim 8 , wherein the patterning of the symmetric stepped trench into the initial asymmetric stepped trench includes:
repeatedly performing an etch process of the upper multi-layered stack using a second slim mask and a slimming process of the second slim mask.

14 . The method of claim 13 , wherein the second slim mask includes an opening, and the opening includes:
a first sidewall that covers one side of the symmetric stepped trench; and a second sidewall that is self-aligned to a lowermost step of the symmetric stepped trench.

15 . A method for forming a semiconductor device, the method comprising:
forming an alternating stack over a substrate that extends from a cell region to a peripheral region of the semiconductor device, the alternating stack including conductive layers and dielectric layers, each of the conductive layers alternating with one of the dielectric layers; etching a first trench in the alternating stack, the first trench having symmetric stepped sidewalls; and etching the first trench to form a second trench with a first stepped sidewall and a second stepped sidewall that is asymmetric to the first stepped sidewall, wherein the second stepped sidewall occupies less surface area of the substrate than the first stepped sidewall.

16 . The method of claim 15 , wherein etching the first trench to form a second trench comprises:
depositing a mask layer over the symmetric stepped sidewalls; etching the mask layer to form an opening in the first trench that exposes a first base of the first trench, the opening being closer to the second sidewall than the first sidewall; and etching the first base of the trench through the opening to expose a second base of the first trench.

17 . The method of claim 15 , wherein etching the first trench separates a plurality of gate pads that extend to the cell region from a plurality of dummy gate pads.

18 . The method of claim 15 , wherein etching the first trench to form a second trench comprises forming a plurality of first steps on the first sidewall and forming a plurality of second steps on the second sidewall, wherein a height of each of the second steps is greater than a height of each of the first steps.

19 . The method of claim 18 , wherein the plurality of first steps and the plurality of second steps occupy a same height in a vertical direction.

Assignees

• Sk Hynix Inc

Inventors

• Kim Eun-Ho
• Jung Eun-Joo
• Yoo Jong-Hyun
• Yun Ki-Jun
• Lee Sung-Hoon

Classifications

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/30

  characterised by the memory core region · CPC title

• H01L27/11565

  Electricity · mapped topic