Semiconductor device

Patent metadata

Field	Value
Publication number	US-2020285536-A1
Application number	US-201916561126-A
Country	US
Kind code	A1
Filing date	Sep 5, 2019
Priority date	Mar 5, 2019
Publication date	Sep 10, 2020
Grant date	—

Abstract

A semiconductor device of an embodiment includes a main circuit configured to perform a predetermined operation to an input signal to output an output signal, an inverse operation circuit configured to receive the output signal of the main circuit as an input, and perform an inverse operation of the predetermined operation by using the output signal to output an inverse operation result signal, and a comparison circuit configured to compare the input signal and the inverse operation result signal, and output a predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an operation circuit configured to perform a predetermined operation to an input signal to output an output signal; an inverse operation circuit configured to receive the output signal as an input, and perform an inverse operation of the predetermined operation by using the output signal to output an inverse operation result signal; and a comparison circuit configured to compare the input signal and the inverse operation result signal, and output a predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.

2 . The semiconductor device according to claim 1 , wherein
the operation circuit performs the predetermined operation at predetermined periods and outputs the output signal, the inverse operation circuit performs the inverse operation and outputs the inverse operation result signal at each of the predetermined periods, and the comparison circuit compares the input signal and the inverse operation result signal at each of the predetermined periods, and outputs the predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.

3 . The semiconductor device according to claim 2 , wherein
the comparative circuit outputs the predetermined signal in end timings of the predetermined periods.

4 . The semiconductor device according to claim 1 , wherein
the operation circuit performs an operation of changing the output signal in response to the input signal, and the inverse operation circuit estimates an estimated value of the input signal based on a change of the output signal, and outputs the estimated value as the inverse operation result signal.

5 . The semiconductor device according to claim 4 , wherein
the output signal is a pulse signal, and the inverse operation circuit performs an operation of estimating the estimated value of the input signal based on timings of rise and fall of the pulse signal.

6 . The semiconductor device according to claim 5 , further comprising:
a clock circuit configured to output a clock signal of a higher frequency than an operation clock of the operation circuit, wherein the inverse operation circuit determines the timings of rise and fall of the pulse signal based on a count value which is counted by using the clock signal.

7 . The semiconductor device according to claim 6 , wherein
the operation circuit receives a threshold signal as the input signal, and outputs a PWM signal as the output signal based on the threshold signal, and the inverse operation circuit outputs the estimated value of the threshold signal by using the count value at a timing of rise of the PWM signal, and the count value at a timing of fall of the PWM signal.

8 . The semiconductor device according to claim 1 , further comprising:
a latch circuit configured to latch the input signal for a predetermined time period, wherein the comparison circuit compares the input signal that is latched by the latch circuit and the inverse operation result signal.

9 . The semiconductor device according to claim 1 , wherein
the input signal is a first comparison value signal that specifies a duty ratio of a PWM signal for motor drive.

10 . The semiconductor device according to claim 1 , wherein
the operation circuit includes an encoder configured to perform encoding as the predetermined operation to the input signal, and the inverse operation circuit includes a decoder configured to perform decoding that is an inverse operation of the encoding by using the output signal.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Nakajima Shigeru

Classifications

• H03M1/1095

  for AC performance, i.e. dynamic testing (H03M1/1085 takes precedence) · CPC title

• G01R31/3167

  Testing of combined analog and digital circuits {(testing ADC's H03M1/1071)} · CPC title

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K5/156

  Arrangements in which a continuous pulse train is transformed into a train having a desired pattern · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title