Methods of fabricating semiconductor devices having crystalline high-k gate dielectric layer

Patent metadata

Field	Value
Publication number	US-2020273700-A1
Application number	US-201916281723-A
Country	US
Kind code	A1
Filing date	Feb 21, 2019
Priority date	Feb 21, 2019
Publication date	Aug 27, 2020
Grant date	—

Abstract

A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.

First claim

1 . A method of fabricating a semiconductor device, comprising:
forming an interfacial layer on a substrate; depositing a gate dielectric layer on the interfacial layer; treating the gate dielectric layer with a first post deposition annealing (PDA) process; depositing a first capping layer on the gate dielectric layer; treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer; removing the first capping layer; treating the gate dielectric layer with a second PDA process; and forming a gate electrode layer on the gate dielectric layer.

2 . The method as claimed in claim 1 , wherein the gate dielectric layer comprises HfO 2 , Al 2 O 3 , ZrO 2 , La 2 O 3 , BaO, TiO 2 , Ta 2 O 5 , Pr 2 O 3 or Y 2 O 3 and is an amorphous gate dielectric layer deposited by an atomic layer deposition (ALD) process, and the first PDA process and the second PDA process crystallize the amorphous gate dielectric layer to form a crystalline gate dielectric layer.

3 . The method as claimed in claim 1 , wherein each of the first PDA process and the second PDA process comprises a soak annealing and a flash annealing that are performed in an NH 3 -containing ambience.

4 . The method as claimed in claim 3 , wherein the NH 3 -containing ambience comprises N 2 and NH 3 , and the ratio of NH 3 in total volume is equal to or below about 10%.

5 . The method as claimed in claim 3 , wherein the soak annealing is performed at a temperature in a range from about 550° C. to about 650° C., and the flash annealing is performed at a temperature in a range from about 950° C. to about 1150° C.

6 . The method as claimed in claim 1 , further comprising:
depositing a second capping layer on the first capping layer after the PMA process; treating the gate dielectric layer by performing a post cap annealing (PCA) process on the second capping layer; and removing the second capping layer before removing the first capping layer.

7 . The method as claimed in claim 6 , wherein the second PDA process is performed on the gate dielectric layer after the second capping layer is removed.

8 . The method as claimed in claim 6 , wherein the first capping layer comprises titanium nitride (TiN) or titanium silicon nitride (TiSiN) and is deposited using an atomic layer deposition (ALD) process, and the second capping layer comprises silicon (Si) and is deposited using a chemical vapor deposition (CVD) process.

9 . The method as claimed in claim 6 , wherein depositing the gate dielectric layer, the first PDA process and the second PDA process are in-situ performed in a first process chamber, and the PMA process and the PCA process are ex-situ performed in a second process chamber.

10 . The method as claimed in claim 1 , wherein the first PDA process and the second PDA process are ex-situ performed in a second process chamber that is different from a first process chamber for depositing the gate dielectric layer.

11 . A method of fabricating a semiconductor device, comprising:
forming an interfacial layer on a substrate in a p-type device region and an n-type device region; depositing an amorphous gate dielectric layer on the interfacial layer; treating the amorphous gate dielectric layer with a post deposition annealing (PDA) process to form a crystalline gate dielectric layer; depositing a capping layer over the crystalline gate dielectric layer; treating the crystalline gate dielectric layer by performing a post cap annealing (PCA) process on the capping layer; removing the capping layer; depositing a p-type work function layer on the crystalline gate dielectric layer in the p-type device region; depositing an n-type work function layer on the crystalline gate dielectric layer in the n-type device region and on the p-type work function layer in the p-type device region; and forming a metal gate fill material over the n-type work function layer in the p-type device region and the n-type device region.

12 . The method as claimed in claim 11 , further comprising treating the crystalline gate dielectric layer with an additional PDA process after the capping layer is removed and before depositing the p-type work function layer.

13 . The method as claimed in claim 12 , wherein each of the PDA process and the additional PDA process comprises a soak annealing performed at a first temperature, and a flash annealing performed at a second temperature that is higher than the first temperature, and the flash annealing is performed after the soak annealing.

14 . The method as claimed in claim 12 , wherein both the PDA process and the additional PDA process are performed in an NH 3 -containing ambience, and the ratio of NH 3 in total volume is equal to or below about 10 %.

15 . The method as claimed in claim 11 , further comprising:
depositing an additional capping layer on the crystalline gate dielectric layer before depositing the capping layer, wherein the additional capping layer comprises titanium nitride (TiN) or titanium silicon nitride (TiSiN); treating the crystalline gate dielectric layer by performing a post metal annealing (PMA) process on the additional capping layer; and removing the additional capping layer.

16 . The method as claimed in claim 15 , wherein the capping layer comprises silicon and is deposited on the additional capping layer using a chemical vapor deposition (CVD) process after the PMA process.

17 - 24 . (canceled)

25 . A method of fabricating a semiconductor device, comprising:
forming an interfacial layer on a substrate; depositing a gate dielectric layer on the interfacial layer; treating the gate dielectric layer with a first post deposition annealing (PDA) process; depositing a first capping layer on the gate dielectric layer; treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer; depositing a second capping layer on the first capping layer; treating the gate dielectric layer by performing a post cap annealing (PCA) process on the second capping layer; removing the first capping layer and the second capping layer; treating the gate dielectric layer with a second PDA process, wherein the gate dielectric layer has an orthorhombic phase and a tetragonal phase after the second PDA process; and forming a gate electrode layer on the gate dielectric layer.

26 . The method as claimed in claim 25 , wherein each of the first PDA process and the second PDA process comprises a soak annealing performed in a first time and a first temperature followed by a flash annealing performed in a second time and a second temperature, the second time is less than the first time, and the second temperature is higher than the first temperature.

27 . The method as claimed in claim 25 , wherein forming the gate electrode layer comprises:
forming a first work function layer over the gate dielectric layer; forming a barrier layer over the first work function layer; and forming a metal gate fill material over the barrier layer.

28 . The method as claimed in claim 27 , wherein forming the metal gate fill material comprises:
conformally depositing a metal film over the barrier layer; and forming a bulk portion of the metal gate fill material on the metal film.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chung-Liang
• Fang Ziwei

Classifications

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/69393

  the material containing tantalum, e.g. Ta2O5 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title