Wiring Layer and Manufacturing Method Therefor

Patent metadata

Field	Value
Publication number	US-2020258914-A1
Application number	US-202016863291-A
Country	US
Kind code	A1
Filing date	Apr 30, 2020
Priority date	Oct 1, 2014
Publication date	Aug 13, 2020
Grant date	—

Abstract

To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a stack of plurality of insulating films; a first conductor; a second conductor; a third conductor; a fourth conductor; and a fifth conductor, wherein two insulating films in the stack of plurality of insulating films are contact with each other via a surface which was polished by a CMP method, wherein the stack of plurality of insulating films comprises a contact hole which passes through the surface, wherein the first conductor is in contact with the second conductor at a bottom of the contact hole, wherein the third conductor is provided in the stack of plurality of insulating films, wherein the first conductor is in contact with a side surface of the third conductor, wherein the fourth conductor is provided over the stack of plurality of insulating films, wherein the first conductor is in contact with the fourth conductor, wherein the fifth conductor is provided in the stack of plurality of insulating films, wherein each of a top surface of the fifth conductor, a side surface of the fifth conductor, and a bottom surface of the fifth conductor is in contact with different insulating films of the stack of plurality of insulating films, and wherein the first conductor is not in contact with the fifth conductor.

2 . The semiconductor device according to claim 1 ,
wherein the fifth conductor is in contact with one insulating film of the stack of plurality of insulating films via a surface on which CMP was performed.

3 . The semiconductor device according to claim 1 ,
wherein the fifth conductor is provided in a different level from the third conductor.

4 . A semiconductor device comprising:
a stack of plurality of insulating films; a first conductor; a second conductor; a third conductor; a fourth conductor; and a fifth conductor, wherein two insulating films in the stack of plurality of insulating films are contact with each other via a surface which was polished by a CMP method, wherein the stack of plurality of insulating films comprises a contact hole which passes through the surface, wherein the first conductor is in contact with the second conductor at a bottom of the contact hole, wherein CMP was performed on a surface of the second conductor via which the second conductor is in contact with the first conductor, wherein the third conductor is provided in the stack of plurality of insulating films, wherein the first conductor is in contact with a side surface of the third conductor, wherein the fourth conductor is provided over the stack of plurality of insulating films, wherein the first conductor is in contact with the fourth conductor, wherein the fifth conductor is provided in the stack of plurality of insulating films, wherein each of a top surface of the fifth conductor, a side surface of the fifth conductor, and a bottom surface of the fifth conductor is in contact with different insulating films of the stack of plurality of insulating films, and wherein the first conductor is not in contact with the fifth conductor.

5 . The semiconductor device according to claim 4 ,
wherein the fifth conductor is in contact with one insulating film of the stack of plurality of insulating films via a surface on which CMP was performed.

6 . The semiconductor device according to claim 4 ,
wherein the fifth conductor is provided in a different level from the third conductor.

Assignees

• Semiconductor Energy Lab

Inventors

• Okazaki Yutaka
• Moriwaka Tomoaki
• Sasagawa Shinya
• Ohtsuki Takashi

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title