Interconnect structures with airgaps arranged between capped interconnects

Patent metadata

Field	Value
Publication number	US-2020227307-A1
Application number	US-201916244387-A
Country	US
Kind code	A1
Filing date	Jan 10, 2019
Priority date	Jan 10, 2019
Publication date	Jul 16, 2020
Grant date	—

Abstract

Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level has a first interconnect, a second interconnect, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first interconnect adjacent to the entrance of the cavity and a second section arranged on the second interconnect adjacent to the entrance of the cavity. A second dielectric layer is formed on the first section of the first dielectric layer and the second section of the first dielectric layer. The second dielectric layer extends from the first section of the first dielectric layer to the second section of the first dielectric layer and across the entrance to the cavity to close an airgap between the first interconnect and the second interconnect.

First claim

What is claimed is:

1 . A structure comprising:
a metallization level including a first interconnect, a second interconnect, and a cavity with an entrance between the first interconnect and the second interconnect; a first dielectric layer including a first section arranged on the first interconnect adjacent to the entrance of the cavity and a second section arranged on the second interconnect adjacent to the entrance of the cavity; and a second dielectric layer on the first section of the first dielectric layer and the second section of the first dielectric layer, the second dielectric layer extending from the first section of the first dielectric layer to the second section of the first dielectric layer and across the entrance to the cavity to close an airgap between the first interconnect and the second interconnect.

2 . The structure of claim 1 wherein the first interconnect has a first top surface with a first surface area, the first section of the first dielectric layer has a first area that is substantially equal to the first surface area of the first interconnect, the second interconnect has a second top surface with a second surface area, and the second section of the first dielectric layer has a second area that is substantially equal to the second surface area of the second interconnect.

3 . The structure of claim 2 wherein the first section of the first dielectric layer is arranged in direct contact with the first interconnect, and the second section of the first dielectric layer is arranged in direct contact with the second interconnect.

4 . The structure of claim 1 wherein the second dielectric layer is comprised of silicon dioxide, hafnium nitride, or aluminum oxide.

5 . The structure of claim 1 wherein the second dielectric layer is comprised of silicon dioxide.

6 . The structure of claim 1 wherein the metallization level includes an interlayer dielectric layer, the first dielectric layer including a third section arranged on the interlayer dielectric layer, and the third section of the first dielectric layer has a different composition than the first section and the second section of the first dielectric layer.

7 . The structure of claim 6 wherein the first section and the second section of the first dielectric layer are comprised of aluminum nitride, the third section of the first dielectric layer is comprised of aluminum oxynitride, and the second dielectric layer is comprised of silicon dioxide.

8 . The structure of claim 1 further comprising:
a third dielectric layer arranged at least in part over the first section and the second section of the first dielectric layer, the third dielectric layer including an opening arranged over the cavity.

9 . The structure of claim 1 wherein the metallization level includes an interlayer dielectric layer having a top surface, the first interconnect and the second interconnect each have a top surface that is substantially coplanar with the top surface of the interlayer dielectric layer, and the top surface of the interlayer dielectric layer is free of the first dielectric layer.

10 . The structure of claim 1 wherein the first interconnect has a first sidewall, the second interconnect has a second sidewall, and the airgap laterally extends from the first sidewall of the first interconnect to the second sidewall of the second interconnect.

11 . The structure of claim 1 wherein the first interconnect has a first sidewall, the second interconnect has a second sidewall, and the first sidewall of the first interconnect and the second sidewall of the second interconnect are free of dielectric material from the second dielectric layer.

12 . A method comprising:
forming a metallization level including a first interconnect and a second interconnect in an interlayer dielectric layer; selectively depositing a first section of a first dielectric layer on a first top surface of the first interconnect and a second section of the first dielectric layer on a second top surface of the second interconnect; after forming the first dielectric layer, removing a first portion of the interlayer dielectric layer to form a cavity with an entrance between the first interconnect and the second interconnect; and selectively depositing a second dielectric layer on the first top surface of the first section of the first dielectric layer and the second section on the second top surface of the first dielectric layer that extends across the entrance to the cavity and closes an airgap defined inside the cavity.

13 . The method of claim 12 wherein the first interconnect includes a first sidewall and the second interconnect includes a second sidewall, the airgap is arranged between the first sidewall of the first interconnect and the second sidewall of the second interconnect, the second dielectric layer is comprised of a dielectric material, and the first sidewall of the first interconnect and the second sidewall of the second interconnect are free of the dielectric material.

14 . The method of claim 13 wherein the cavity has a bottom arranged between the first sidewall of the first interconnect and the second sidewall of the second interconnect, and the dielectric material deposits on the interlayer dielectric layer at the bottom of the cavity.

15 . The method of claim 12 wherein the first dielectric layer includes a third section on a second portion of the interlayer dielectric layer, the third section of the first dielectric layer has a different composition from the first section and the second section of the first dielectric layer, and further comprising:
removing the third section of the first dielectric layer selective to the first section and the second section of the first dielectric layer.

16 . The method of claim 12 wherein the second dielectric layer is comprised of silicon dioxide, hafnium nitride, or aluminum oxide.

17 . The method of claim 12 further comprising:
depositing a third dielectric layer arranged at least in part over the first section and the second section of the first dielectric layer,
wherein the third dielectric layer includes an opening arranged over the first portion of the interlayer dielectric layer.

18 . The method of claim 12 further comprising:
polishing the first section of the first dielectric layer, the second section of the first dielectric layer, and the second dielectric layer to provide respective top surfaces that are substantially planar with the second dielectric layer laterally arranged between the first section of the first dielectric layer and the second section of the first dielectric layer.

19 . The method of claim 12 further comprising:
depositing a third dielectric layer arranged at least in part over the first section and the second section of the first dielectric layer,
wherein the third dielectric layer includes an opening arranged over the first portion of the interlayer dielectric layer, and the third dielectric layer is arranged in part between the second dielectric layer and the first section and the second section of the first dielectric layer.

20 . The method of claim 12 wherein removing the first portion of the interlayer dielectric layer to form the cavity with the entrance between the first interconnect and the second interconnect comprises:
damaging the first portion of the interlayer dielectric layer; and
etching the first portion of the interlayer dielectric layer selective to a second portion of the interlayer dielectric layer beneath the first portion of the in

Assignees

• Globalfoundries Inc

Inventors

• Licausi Nicholas V

Classifications

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title