Multiple stage gate drive for cascode current sensing

Patent metadata

Field	Value
Publication number	US-2020220476-A1
Application number	US-202016821013-A
Country	US
Kind code	A1
Filing date	Mar 17, 2020
Priority date	Jun 12, 2017
Publication date	Jul 9, 2020
Grant date	—

Abstract

A power converter comprising an energy transfer element is coupled between an input of the power converter and an output of the power converter. A cascode circuit generates a first sense signal and a second sense signal. A controller controls the switching of the cascode circuit to transfer energy from the input of the power converter to the output of the power converter. The controller comprising a current sense circuit generates a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal. A control circuit generates a control signal in response to the current limit signal and the overcurrent signal. A drive circuit comprising a first stage gate drive circuit generates a drive signal in response to the control signal to reduce EMI, and a second stage of gate drive circuit to enable accurate current sensing of the cascode circuit.

First claim

What is claimed is:

1 . A power converter, comprising:
an energy transfer element coupled between an input of the power converter and an output of the power converter; a cascode circuit coupled to the energy transfer element, the cascode circuit further configured to generate a first sense signal and a second sense signal; and a controller coupled to control switching of the cascode circuit to transfer energy from the input of the power converter to the output of the power converter, the controller comprising:
a current sense circuit configured to generate a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal;
a control circuit configured to generate a control signal in response to the current limit signal and the overcurrent signal; and
a drive circuit comprising a multiple stage gate drive circuit configured to generate a drive signal in response to the control signal, wherein a first stage of the multiple stage gate drive circuit is configured to provide the drive signal to reduce EMI, and a second stage of the multiple stage gate drive circuit is configured to provide the drive signal to enable accurate current sensing of the cascode circuit.

2 . The power converter of claim 1 , the cascode circuit comprising:
a normally-on switch; and a control switch coupled to the normally-on switch.

3 . The power converter of claim 1 , wherein the first sense signal is generated by a drain of a first sense finger of a control switch and a first current source.

4 . The power converter of claim 1 , wherein the second sense signal is generated by a drain terminal of a second sense finger of a control switch coupled to a second current source.

5 . The power converter of claim 2 , the current sense circuit further coupled to receive a source signal generated by a source terminal of the normally-on switch.

6 . The power converter of claim 5 , the current sense circuit comprising:
a first comparator configured to generate the current limit signal in response to the source signal being greater than the first sense signal; and a second comparator configured to generate the overcurrent signal in response to the source signal being greater than the second sense signal.

7 . The power converter of claim 5 , the drive circuit comprising:
a first transistor configured to generate the drive signal of the first stage of the multiple stage gate drive circuit in response to the control signal; a delay circuit configured to generate a delay signal in response to the control signal; and a second transistor configured to generate the drive signal of the second stage of the multiple stage gate drive circuit in response to the delay signal.

8 . The power converter of claim 2 , wherein the normally-on switch is a JFET.

9 . The power converter of claim 8 , wherein the normally-on switch comprises of silicon carbide material.

10 . The power converter of claim 2 , wherein the normally-on switch comprises of gallium nitride (GaN) material.

11 . The power converter of claim 2 , wherein the normally-on switch is a high electron mobility transistor (HEMT).

12 . A controller configured for use in a power converter, comprising:
a current sense circuit configured to generate a current limit signal in response to a first sense signal representative of a switch current of a control switch, the current sense circuit further configured to generate an overcurrent signal in response to a second sense signal for regulating an output voltage of the power converter; a control circuit configured to generate a control signal in response to the current limit signal and the overcurrent signal; and a drive circuit configured to generate a drive signal for a cascode circuit in response to the control signal by use of a multiple stage gate drive circuit, wherein the drive signal provided by a first stage of the multiple stage gate drive circuit is configured to reduce EMI, and wherein the drive signal provided by a second stage of the multiple stage gate drive circuit is configured to enable current sensing of the cascode circuit.

13 . The controller of claim 12 , the current sense circuit comprising:
a first comparator configured to generate the current limit signal in response to a source signal of the cascode circuit being greater than the first sense signal; and a second comparator configured to generate the overcurrent signal in response to the source signal being greater than the second sense signal.

14 . The power converter of claim 12 , the drive circuit comprising:
a first transistor configured to generate the drive signal of the first stage of the multiple stage gate drive circuit in response to the control signal; a delay circuit configured to generate a delay signal in response to the control signal; and a second transistor configured to generate the drive signal of the second stage of the multiple stage gate drive circuit in response to the delay signal.

15 . A controller configured for use in a power converter, comprising:
a current sense circuit coupled to receive a first sense signal representative of a switch current of a control switch of a cascode circuit and a second sense signal for regulating an output voltage of the power converter of the control switch; and a drive circuit configured to generate a drive signal for the cascode circuit by use of a multiple stage gate drive circuit, wherein the drive signal provided by a first stage of the multiple stage gate drive circuit is configured to reduce EMI, and wherein the drive signal provided by a second stage of the multiple stage gate drive circuit is configured to enable current sensing of the cascode circuit.

16 . The controller of claim 15 , wherein a resistance of the first sense signal and the second sense signal is at a nominal value in response to the second stage of the multiple stage gate drive circuit.

17 . The controller of claim 15 , wherein the current sense circuit is configured to generate a current limit signal in response to the first sense signal, the current sense circuit further configured to generate an overcurrent signal in response to the second sense signal.

18 . The controller of claim 17 , further comprising a control circuit configured to generate a control signal in response to the current limit signal and the overcurrent signal.

19 . The controller of claim 18 , wherein the drive circuit is configured to generate the drive signal in response to the control signal.

Assignees

• Power Integrations Inc

Inventors

• Duvnjak Rajko

Classifications

• H02H7/1227 Primary

  responsive to abnormalities in the output circuit, e.g. short circuit · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title

• G01R19/0092

  Measuring current only · CPC title

• H02M3/33507

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title