Semiconductor package having a sidewall connection

Patent metadata

Field	Value
Publication number	US-2020211988-A1
Application number	US-201916706594-A
Country	US
Kind code	A1
Filing date	Dec 6, 2019
Priority date	Dec 28, 2018
Publication date	Jul 2, 2020
Grant date	—

Abstract

A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.

First claim

1 . A device, comprising:
a semiconductor die including a first surface and a second surface that is transverse to the first surface; a contact pad on the first surface of the semiconductor die; a redistribution layer on the first surface of the semiconductor die and the contact pad, the redistribution layer having an extended portion extending from the contact pad to the second surface of the semiconductor die, the extended portion including a first electrical contact on the second surface of the semiconductor die; and a conductive structure on the redistribution layer spaced from the contact pad, the conductive structure including a second electrical contact on the first surface of the semiconductor die.

2 . The device of claim 1 , wherein the second electrical contact includes an under bump metallization, a solder ball or a solder bump.

3 . The device of claim 1 , wherein the first electrical contact and the second electrical contact provide distinct electrical signals from each other.

4 . The device of claim 1 , wherein the semiconductor die includes a third surface opposite the first surface, and the extended portion extends past the first surface to the third surface of the semiconductor die.

5 . The device of claim 1 , wherein the extended portion covers the second surface from the first surface to a third surface of the semiconductor die.

6 . The device of claim 1 , further comprising:
a passivation layer between the redistribution layer and the semiconductor die, the passivation layer overlapping a first portion of the contact pad.

7 . The device of claim 6 , further comprising:
a first dielectric layer between the redistribution layer and the passivation layer, the first dielectric layer overlapping a second portion of the contact pad, the second portion being between the first portion and a third portion of the contact pad that is in contact with the redistribution layer.

8 . The device of claim 7 , further comprising:
a second dielectric layer on the redistribution layer; and the conductive structure, including:
a metallization layer on the redistribution layer spaced apart from the contact pad.

9 . The device of claim 1 , further comprising:
a mold protection layer between the second surface of the semiconductor die and the extended portion of the redistribution layer.

10 . A device, comprising:
a first semiconductor die including a first surface, a second surface and a third surface; a first redistribution layer on the first surface of the first semiconductor die, the first redistribution layer having an extended portion extending from the first surface to the second surface; a second semiconductor die including a fourth surface, a fifth surface and a sixth surface, the fourth surface of the second semiconductor die facing the third surface of the first semiconductor die; a second redistribution layer on the sixth surface of second semiconductor, the second redistribution layer having an extended portion extending from the sixth surface to the fifth surface.

11 . The device of claim 10 , further comprising:
a conductive connection electrically connecting the first redistribution layer and the second redistribution layer.

12 . The device of claim 11 , wherein the conductive connection includes a solder bump, a solder joint, a solder ball, or a wire bonding.

13 . The device of claim 10 , wherein the second surface of the first semiconductor die and the fifth surface of the semiconductor die is coplanar.

14 . A method, comprising:
forming a contact pad on a first surface of a first semiconductor die; forming a first redistribution layer on the first surface of the first semiconductor die and the contact pad, including:
forming an extended portion of the first redistribution layer extending from the contact pad to a second surface of the first semiconductor die, the second surface being transverse to the first; and
forming a conductive structure on the first redistribution layer spaced apart from the contact pad.

15 . The method of claim 14 , further comprising:
forming a second redistribution layer on a fourth surface of a second semiconductor die, including forming an extended portion of the second redistribution layer extending from the fourth surface to a fifth surface of the second semiconductor die, forming an adhesive layer between the first semiconductor die and the second semiconductor die.

16 . The method of claim 15 , further comprising:
forming the extended portion of the first redistribution layer on the second surface of the first semiconductor die and the extended portion of the second redistribution layer on the fifth surface of the second semiconductor die, the extended portions of the first and second redistribution layers being aligned.

Assignees

• St Microelectronics Ltd

Inventors

• Jahja Endruw
• Su Cheng-Yang

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title