Semicondcutor package and method of dicing semiconductor device

Patent metadata

Field	Value
Publication number	US-2020203270-A1
Application number	US-201816231614-A
Country	US
Kind code	A1
Filing date	Dec 24, 2018
Priority date	Dec 24, 2018
Publication date	Jun 25, 2020
Grant date	—

Abstract

A semiconductor package includes a semiconductor device, an encapsulating material, and a redistribution structure. The semiconductor device includes a chamfer disposed on one of a plurality of side surfaces of the semiconductor device. The encapsulating material encapsulates the semiconductor device. The redistribution structure is disposed over the encapsulating material and electrically connected to the semiconductor device.

First claim

1 . A semiconductor package, comprising:
a semiconductor device comprising a chamfer disposed on one of a plurality of side surfaces of the semiconductor device; an encapsulating material encapsulating the semiconductor device; a redistribution structure disposed over the encapsulating material and electrically connected to the semiconductor device.

2 . The semiconductor package as claimed in claim 1 , wherein the chamfer comprises a bevel corner or a rounding corner connected between adjacent two of the plurality of side surfaces of the semiconductor device.

3 . The semiconductor package as claimed in claim 1 , wherein the encapsulating material encapsulating the chamfer.

4 . The semiconductor package as claimed in claim 1 , wherein the redistribution structure comprises a circuit board.

5 . The semiconductor package as claimed in claim 1 , wherein the encapsulating material comprises an underfill encapsulating at least a part of the plurality of side surfaces and filling between the semiconductor device and the redistribution structure.

6 . The semiconductor package as claimed in claim 4 , wherein the encapsulating material comprises a molding compound, and an upper surface of the encapsulating material is substantially coplanar with an upper surface of the semiconductor device.

7 . The semiconductor package as claimed in claim 6 , further comprising a heat sink disposed over the upper surface of the encapsulating material and the upper surface of the semiconductor device and a plurality of locking components extending through the heat sink, the encapsulating material and the redistribution structure and located in the chamfer.

8 . The semiconductor package as claimed in claim 1 , wherein the chamfer is a concave.

9 . The semiconductor package as claimed in claim 8 , further comprising an electrical component disposed in the concave, wherein the encapsulating material encapsulating the electrical component.

10 . The semiconductor package as claimed in claim 1 , wherein the redistribution structure comprises a redistribution circuit layer and a dielectric layer disposed alternately with each other.

11 . A semiconductor package, comprising:
a semiconductor device comprising a concave disposed on one of a plurality of side surfaces of the semiconductor device; an electrical component disposed on a side of the semiconductor device and at least partially located in the concave; an encapsulating material encapsulating the semiconductor device and the electrical component; a redistribution structure disposed over the encapsulating material and electrically connected to the semiconductor device and the electrical component.

12 . The semiconductor package as claimed in claim 11 , wherein the concave is disposed at a corner of the semiconductor device and connected between adjacent two of the plurality of side surfaces of the semiconductor device.

13 . The semiconductor package as claimed in claim 11 , wherein the semiconductor device comprises a plurality of semiconductor devices arranged in a side by side manner, the concaves of adjacent two of the semiconductor devices are corresponding to each other and jointly define a receiving space, and the electrical component is disposed in the receiving space.

14 . The semiconductor package as claimed in claim 11 , wherein the electrical component comprises a passive device, an electrical interconnect, or an optical device.

15 . The semiconductor package as claimed in claim 11 , wherein the redistribution structure comprises a redistribution circuit layer and a dielectric layer disposed alternately with each other.

16 . A method of forming a semiconductor device, comprising:
providing a wafer comprising a plurality of semiconductor device units connecting to one another; forming a chamfer cut at each of the plurality of semiconductor device units; and dicing the plurality of semiconductor device units along a plurality of scribing lines to form a plurality of semiconductor devices independent from one another.

17 . The method of dicing the semiconductor device as claimed in claim 16 , wherein the chamfer cut is a curvy line at a corner of each of the plurality of semiconductor device units.

18 . The method of dicing the semiconductor device as claimed in claim 16 , wherein the plurality of scribing lines are straight lines, and one of the plurality of scribing lines connects the chamfer cut at each of the plurality of semiconductor device units.

19 . The method of dicing the semiconductor device as claimed in claim 16 , wherein the plurality of scribing lines are straight lines, and one of the plurality of scribing lines extending through the chamfer cut at each of the plurality of semiconductor device units.

20 . The method of dicing the semiconductor device as claimed in claim 16 , wherein the chamfer cut is formed by laser cutting or plasma etching, and the plurality of scribing lines are diced by a blade.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Chung-Shi
• Hsieh Ching-Hua
• Yu Chen-Hua
• Liao Hsin-Hung
• Hwang Chien-Ling
• Wu Sung-Yueh

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W90/00

  Package configurations · CPC title