Systems and techniques for accessing multiple memory cells concurrently

Patent metadata

Field	Value
Publication number	US-2020202928-A1
Application number	US-201916712682-A
Country	US
Kind code	A1
Filing date	Dec 12, 2019
Priority date	Dec 19, 2018
Publication date	Jun 25, 2020
Grant date	—

Abstract

Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

First claim

1 . A method, comprising:
identifying a first memory cell of a memory tile to read; identifying a second memory cell of the memory tile to read; selecting a first polarity of a first read pulse to read the first memory cell and a second polarity of a second read pulse to read the second memory cell; reading the first memory cell using the first read pulse; and reading the second memory cell using the second read pulse concurrently with reading the first memory cell based at least in part on selecting the first polarity and the second polarity.

2 . The method of claim 1 , wherein the first polarity of the first read pulse is opposite the second polarity of the second read pulse.

3 . The method of claim 1 , further comprising:
applying voltages to access lines coupled with the first memory cell and the second memory cell concurrently based at least in part on selecting the first polarity and the second polarity, wherein reading the second memory cell concurrently with the first memory cell is based at least in part on applying the voltages to the access lines.

4 . The method of claim 3 , further comprising:
partitioning the first read pulse into a first voltage to apply to a first access line and a second voltage to apply to a second access line, the first access line and the second access line coupled with the first memory cell; identifying a magnitude and a polarity of the first voltage based at least in part on the first polarity of the first read pulse; and identifying, based at least in part on the first polarity of the first read pulse and the first voltage, a magnitude of the second voltage different than the magnitude of the first voltage and a polarity of the second voltage different than the polarity of the first voltage, wherein applying the voltages is based at least in part on the partitioning and the identifying.

5 . The method of claim 1 , further comprising:
identifying a first logic state stored on the first memory cell and a second logic state stored on the second memory cell based at least in part reading the second memory cell concurrently with reading the first memory cell.

6 . The method of claim 1 , further comprising:
coupling the first memory cell to a first type of sense component based at least in part on the first read pulse having the first polarity; and coupling the second memory cell to a second type of sense component different than the first type based at least in part on the second read pulse having the second polarity.

7 . The method of claim 1 , wherein the first polarity and the second polarity are selected such that a voltage difference caused by the first read pulse or the second read pulse at a third memory cell of the memory tile does not satisfy a programming threshold of the third memory cell.

8 . The method of claim 1 , further comprising:
determining that the first memory cell and the second memory cell are coupled with a common access line, wherein the first polarity and the second polarity are the same based at least in part on determining that the first memory cell and the second memory cell are coupled with the common access line.

9 . A method, comprising:
identifying a first memory cell of a memory tile to program using a write operation; identifying a second memory cell of the memory tile to access using a write operation or a read operation; determining that accessing the second memory cell concurrently with programming the first memory cell is permitted on the memory tile during an access operation duration; programming the first memory cell of the memory tile during the access operation duration; and accessing the second memory cell of the memory tile concurrently with programming the first memory cell during the access operation duration based at least in part on determining that accessing the second memory cell concurrently with programming the first memory cell is permitted.

10 . The method of claim 9 , wherein accessing the second memory cell concurrently with programming the first memory cell comprises programming the first memory cell using a first programming pulse during the access operation duration and programming the second memory cell using a second programming pulse during the access operation duration concurrently with programming the first memory cell.

11 . The method of claim 10 , further comprising:
delaying an application of the first programming pulse or the second programming pulse during the access operation duration based at least in part on a voltage applied to an unselected memory cell exceeding a programming threshold on the memory tile during the access operation duration, wherein accessing the second memory cell concurrently with programming the first memory cell during the access operation duration is based at least in part on delaying the first programming pulse.

12 . The method of claim 11 , further comprising:
identifying a first bit transition of the first memory cell during the write operation and a second bit transition of the second memory cell during the write operation; and determining that a combination of the first bit transition and the second bit transition is would result in the voltage applied to the unselected memory cell exceeding the programming threshold on the memory tile during the access operation duration, wherein delaying the application of the first programming pulse or the second programming pulse is based at least in part on determining that the combination of the first bit transition and the second bit transition would result in the voltage applied to the unselected memory cell exceeding the programming threshold.

13 . The method of claim 10 , further comprising:
refraining from applying the first programming pulse or the second programming pulse during the access operation duration based at least in part on a combination of the first programming pulse and the second programming pulse applying a voltage to an unselected memory cell that exceeds a programming threshold of the unselected memory cell.

14 . The method of claim 9 , further comprising:
determining that the first memory cell is coupled with different access lines than the second memory cell, wherein accessing the second memory cell concurrently with programming the first memory cell during the access operation duration is based at least in part on determining that the first memory cell is coupled with different access lines than the second memory cell.

15 . The method of claim 9 , wherein accessing the second memory cell concurrently with programming the first memory cell comprises programming the first memory cell using a programming pulse during the access operation duration and reading the second memory cell using a read pulse during the access operation duration concurrently with programming the first memory cell.

16 . The method of claim 15 , further comprising:
selecting a polarity of the read pulse applied to the second memory cell during the access operation duration based at least in part on a characteristic of the programming pulse applied to the first memory cell during the access operation duration.

17 . The method of claim 16 , wherein the characteristic of the programming pulse is a polarity of the programming pulse, a location to which the programming pulse is being applied, a bit transition associated with the programming pulse, or a combination thereof.

18 . The method of claim 15 , further comprising:
inverting data read from the second memory cell based at least in part on the read pulse having a negative polarity; and

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/003 Primary

  Cell access · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C2013/0088

  Write with the simultaneous writing of a plurality of cells · CPC title