Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

Patent metadata

Field	Value
Publication number	US-2020201807-A1
Application number	US-201916720976-A
Country	US
Kind code	A1
Filing date	Dec 19, 2019
Priority date	Dec 19, 2018
Publication date	Jun 25, 2020
Grant date	—

Abstract

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

First claim

I/we claim:

1 . An apparatus comprising:
a plurality of memory devices; a buffering device including:
memory interface circuitry, and
at least one first-in first-out (FIFO) circuit or multiplexer circuit; and
a parallel bus operably connecting the buffering device to the plurality of memory devices, the parallel bus including:
a plurality of independent control lines, each of the plurality of independent control lines operably coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices, and
a plurality of independent data channels, each of the plurality of independent data channels operably coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

2 . The apparatus of claim 1 , wherein each of the first subsets of the plurality of memory devices includes memory devices of a single memory type.

3 . The apparatus of claim 1 , wherein each of the second subsets of the plurality of memory devices includes memory devices having different memory types.

4 . The apparatus of claim 3 , wherein the different memory types comprise one or more of NAND, NOR, phase change memory (PCM), magnetoresistive memory (MRAM), DRAM, SRAM, and ferroelectric memory.

5 . The apparatus of claim 1 , wherein the buffering device includes a channel interface configured to communicate with a connected host device using a DDR 5 protocol.

6 . The apparatus of claim 1 , wherein the memory interface circuitry is configured to perform processing in memory functions in one or more of the plurality of memory devices.

7 . The apparatus of claim 1 , wherein the memory interface circuitry is configured to perform atomic memory functions in one or more of the plurality of memory devices.

8 . The apparatus of claim 1 , wherein the plurality of memory devices includes chip scale packaging memory devices.

9 . The apparatus of claim 1 , wherein the plurality of memory devices includes one or more memory devices lacking error correcting code (ECC) circuitry, and further wherein the memory interface circuitry is to perform error correcting in the one or more memory devices.

10 . The apparatus of claim 1 , wherein the buffering device is configured to map physical addresses of the plurality of memory devices to logical addresses.

11 . The apparatus of claim 1 , wherein the buffering device is configured to remap physical addresses of the plurality of memory devices in response to the detection of a bad bit in one or more of the plurality of memory devices.

12 . A method, comprising:
receiving a plurality of signals at a buffering device of an apparatus, the plurality of signals including command/address signals and data signals; directing, with memory interface circuitry of the buffering device, the command/address signals via a plurality of independent control lines to a first subset of a plurality memory devices of the apparatus; directing, with at least one first-in first-out (FIFO) circuit or multiplexer circuit of the buffering device, the data signals via a plurality of independent data channels to a second subset of the plurality of memory devices.

13 . The method of claim 12 , wherein the first subset of the plurality of memory devices includes memory devices of a single memory type.

14 . The method of claim 12 , wherein the second subset of the plurality of memory devices includes memory devices having different memory types.

15 . The method of claim 14 , wherein the different memory types comprise one or more of NAND, NOR, phase change memory (PCM), magnetoresistive memory (MRAM), DRAM, SRAM, and ferroelectric memory.

16 . The method of claim 12 , wherein the plurality of signals is communicated from a connected host device using a DDRS protocol.

17 . The method of claim 12 , further comprising performing, with the memory interface circuitry, processing-in-memory functions in one or more of the plurality of memory devices.

18 . The method of claim 12 , further comprising performing, with the memory interface circuitry, atomic memory functions in one or more of the plurality of memory devices.

19 . The method of claim 13 , wherein the plurality of memory devices includes chip scale packaging memory devices.

20 . The method of claim 13 , wherein the plurality of memory devices includes one or more memory devices lacking error correcting code (ECC) circuitry, and further comprising performing, with the memory interface circuitry, error correcting functions in the one or more memory devices.

21 . The method of claim 12 , further comprising mapping, with the buffering device, physical addresses of the plurality of memory devices to logical addresses.

22 . The method of claim 12 , further comprising remapping, with the buffering device, physical addresses of the plurality of memory devices in response to the detection of a bad bit in one or more of the plurality of memory devices.

23 . An apparatus, comprising:
a plurality of memory devices arranged into a first channel and a second channel; first and second buffering devices corresponding to the first and second channels, respectively, each buffering device including:
memory interface circuitry, and
at least one first-in first-out (FIFO) circuit or multiplexer circuit; and
a parallel bus operably connecting the first and second buffering device to memory devices of the first and second channels, respectively, the parallel bus including:
a plurality of independent control lines, each of the plurality of independent control lines operably coupling the memory interface circuitry of one of the first and second buffering devices to a corresponding subset of a plurality of first subsets of the plurality of memory devices, and
a plurality of independent data channels, each of the plurality of independent data channels operably coupling the at least one FIFO circuit or multiplexer circuit of one of the first and second buffering devices to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Assignees

• Micron Technology Inc

Inventors

• Kinsley Thomas H
• Pax George E
• Hollis Timothy M
• Sharma Yogesh
• Richards Randon K
• Yoo Chan H
• King Gregory A
• Stave Eric J

Classifications

• G06F13/1684

  using multiple buses · CPC title

• G06F5/06

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F13/4234 Primary

  being a memory bus · CPC title

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title