Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication

Patent metadata

Field	Value
Publication number	US-2020194559-A1
Application number	US-201916705863-A
Country	US
Kind code	A1
Filing date	Dec 6, 2019
Priority date	May 17, 2005
Publication date	Jun 18, 2020
Grant date	—

Abstract

A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.

First claim

What is claimed is:

1 . A semiconductor structure comprising:
a photonic structure; and a first crystalline semiconductor disposed above the photonic structure, wherein a surface of the first crystalline semiconductor comprises a plurality of ridges, wherein a width of one ridge of the plurality of ridges is less than or equal to a visible light wavelength, and wherein a spacing of the plurality of ridges is less than or equal to the visible light wavelength.

2 . The semiconductor structure of claim 1 , further comprising a metal contact disposed on the first crystalline semiconductor.

3 . The semiconductor structure of claim 2 , wherein the metal contact conforms to at least one ridge.

4 . The semiconductor structure of claim 1 , further comprising a metal layer disposed on a surface of the photonic structure opposite the first crystalline semiconductor.

5 . The semiconductor structure of claim 1 , wherein top surfaces of the plurality of ridges are (100) surfaces.

6 . The semiconductor structure of claim 1 , wherein top surfaces of the plurality of ridges are coplanar.

7 . The semiconductor structure of claim 1 , wherein the photonic structure comprises a light-emitting diode (LED), wherein the spacing of the plurality of ridges is about equal to a wavelength of visible light emitted by the LED.

8 . The semiconductor structure of claim 1 , further comprising a second crystalline semiconductor disposed between the first crystalline semiconductor and the photonic structure, wherein the second crystalline semiconductor has a smaller bandgap than the first crystalline semiconductor.

9 . A device comprising:
a first metal contact layer disposed on a first side of a substrate; a reflective layer disposed on a second side of the substrate, the second side being opposite the first side; a photonic layer disposed on the reflective layer, the photonic layer comprising at least one photonic semiconductor device; a crystalline semiconductor material disposed on the photonic layer, the crystalline semiconductor material comprising a first crystalline semiconductor having a first bandgap and a second crystalline material having a second bandgap, wherein the first crystalline semiconductor is closer to the photonic layer than the second crystalline semiconductor, wherein the first bandgap is smaller than the second bandgap, wherein the crystalline semiconductor material comprises first regions having a first thickness and second regions having a second thickness that is less than the first thickness, wherein the first regions protrude above the second regions; and a second metal contact layer extending on the first regions and the second regions of the crystalline semiconductor material.

10 . The device of claim 9 , wherein the reflective layer is a layer of aluminum.

11 . The device of claim 9 , wherein adjacent first regions are separated by a distance that is less than or equal to a visible light wavelength.

12 . The device of claim 9 , wherein adjacent second regions are separated by a distance that is less than or equal to a visible light wavelength.

13 . The device of claim 9 , wherein the at least one photonic semiconductor device comprises a photovoltaic device.

14 . The device of claim 9 , wherein the first regions extend over the photonic layer in a first direction.

15 . The device of claim 9 , wherein the crystalline semiconductor material further comprises a third crystalline semiconductor having a third bandgap, wherein the second crystalline semiconductor is closer to the photonic layer than the third crystalline semiconductor, wherein the second bandgap is smaller than the third bandgap.

16 . The device of claim 9 , wherein the first regions comprise a two-dimensional array of raised features protruding above the second regions.

17 . A device comprising:
a photonic structure disposed on a substrate, the photonic structure comprising one or more semiconductor layers, the photonic structure having a top surface that is planar; a crystalline semiconductor material on the top surface of the photonic structure; and a plurality of dielectric regions on the crystalline semiconductor material, wherein the dielectric regions are laterally separated, wherein the dielectric regions extend on the crystalline semiconductor material in a first direction, wherein portions of the crystalline semiconductor material covered by the dielectric regions have a top surface that is a first distance above the photonic structure, wherein portions of the crystalline semiconductor material that are free of the dielectric regions have a have a top surface that is a second distance above the photonic structure that is greater than the first distance; and a metal contact extending on the crystalline semiconductor material in a second direction that is orthogonal to the first direction.

18 . The device of claim 17 , wherein the dielectric regions protrude above the crystalline semiconductor material.

19 . The device of claim 17 , wherein top surfaces of the dielectric regions are coplanar with top surfaces of the crystalline semiconductor material.

20 . The device of claim 17 , wherein the crystalline semiconductor material comprises a crystalline semiconductor having a first composition disposed on a crystalline semiconductor having a second composition that is different from the first composition.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Jizhong
• Lochtefeld Anthony J

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/2926

  Crystal orientations · CPC title