Semiconductor device

Patent metadata

Field	Value
Publication number	US-2020194500-A1
Application number	US-202016802976-A
Country	US
Kind code	A1
Filing date	Feb 27, 2020
Priority date	Jul 6, 2017
Publication date	Jun 18, 2020
Grant date	—

Abstract

A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

First claim

1 - 19 . (canceled)

20 . A method for fabricating a semiconductor device, the method comprising:
forming a first memory cell extending in a first direction and including a first phase change memory and a first ovonic threshold switch (OTS); forming a first capping film along sidewalls of the first memory cell at a first temperature; and forming a second capping film directly on the first capping film at a second temperature higher than the first temperature.

21 . The method of claim 20 , wherein forming the first capping film and forming the second capping film are performed in-situ.

22 . The method of claim 20 , wherein the first capping film is formed through a first plasma process using a N 2 gas without a NH 3 gas.

23 . The method of claim 20 , wherein the second capping film is formed through a second plasma process using a NH 3 gas.

24 . The method of claim 23 , wherein the second plasma process includes:
performing a first sub plasma process using a N 2 gas; and performing a second sub plasma process using the NH 3 gas, after the first sub plasma process.

25 . The method of claim 20 , wherein each of the first and second capping films includes at least one of SiN, SiON, SiCN, and SiBN.

26 . The method of claim 20 , further comprising:
forming a second memory cell extending in the first direction and including a second phase change memory and a second OTS while the first memory cell is formed, wherein the second memory cell is spaced apart from the first memory cell in a second direction intersecting the first direction, wherein the first capping film is continuous in the first direction along the sidewalls of the first memory cell and sidewalls of the second memory cell, and in the second direction between the sidewalls of the first and second memory cells, and wherein the second capping film entirely fills a space between the first and second memory cells.

27 . The method of claim 20 , wherein:
first memory cell includes an upper electrode and a lower electrode disposed with the first phase change memory and the first OTS interposed therebetween, and the first capping film and the second capping film do not cover an upper surface of the upper electrode.

28 . A method for fabricating a semiconductor device, the method comprising:
forming a first memory cell extending in a first direction and including a first phase change memory and a first ovonic threshold switch (OTS); forming a first capping film along sidewalls of the first memory cell using a first N 2 plasma; and forming a second capping film on the first capping film using a second N 2 plasma and a NH 3 plasma, wherein the NH 3 plasma is not used while the first capping film is formed.

29 . The method of claim 28 , wherein the second capping film is formed at a higher temperature than the first capping film.

30 . The method of claim 28 , wherein forming the second capping film proceeds in-situ in succession to forming the first capping film.

31 . The method of claim 30 , wherein the second capping film is formed directly on the first capping film.

32 . The method of claim 28 , wherein:
forming the first capping film includes a dose operation, a first purge operation, a radio frequency (RF) plasma operation, and a second purge operation which are performed successively, and the RF plasma operation uses the first N 2 plasma.

33 . The method of claim 28 , wherein:
forming o the second capping film includes a dose operation, a first purge operation, a radio frequency (RF) plasma operation, a NH 3 processing operation, and a second purge operation which are performed successively, the RF plasma operation uses the second N 2 plasma, and the NH 3 processing operation uses the NH 3 plasma.

34 . The method of claim 28 , further comprising:
forming a second memory cell extending in the first direction and including a second phase change memory and a second OTS while the first memory cell is formed, wherein the second memory cell is spaced apart from the first memory cell in a second direction intersecting the first direction, wherein the first capping film is continuous in the first direction along the sidewalls of the first memory cell and sidewalls of the second memory cell, and in the second direction between the sidewalls of the first and second memory cells, and wherein the second capping film entirely fills a space between the first and second memory cells.

35 . A method for fabricating a semiconductor device, the method comprising:
forming a lower electrode and a molding film surrounding the lower electrode, the molding film including SiN; forming a phase change memory, an ovonic threshold switch (OTS) and an upper electrode, the phase change memory and the OTS being disposed between the lower electrode and the upper electrode; forming a first capping film at a first temperature, the first capping film extending along sidewalls of the phase change memory, sidewalls of the OTS, sidewalls of the upper electrode, and an upper surface of the upper electrode; forming a second capping film directly on the first capping film at a second temperature higher than the first temperature; and removing a portion of the second capping film and a portion of the first capping film to expose the upper surface of the upper electrode, wherein each of the first and second capping films includes a nitride-based insulating material.

36 . The method of claim 35 , wherein the first capping film is formed through a first plasma process using a N 2 gas without a NH 3 gas.

37 . The method of claim 35 , wherein:
the second capping film is formed through a second plasma process using a NH 3 gas, and the second plasma process includes:
performing a first sub plasma process using a N 2 gas; and
performing a second sub plasma process using the NH 3 gas after the first sub plasma process.

38 . The method of claim 35 , wherein each of the first and second capping films includes at least one of SiN, SiON, SiCN, and SiBN.

39 . The method of claim 35 , wherein the first capping film extends continuously between an upper surface of the mold film and a bottom surface of the second capping film.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong Uk
• Park Jeong Hee
• Park Seong Geon
• Park Soon Oh
• Lee Jung Moo

Classifications

• H10N70/821

  Device geometry · CPC title

• H10B41/30

  characterised by the memory core region · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/231 Primary

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/00 Primary

  Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching (integrated devices or assemblies of multiple devices H10N79/00) · CPC title