Die backside structures for enhancing liquid cooling of high power multi-chip package (mcp) dice

Patent metadata

Field	Value
Publication number	US-2020176352-A1
Application number	US-201716612340-A
Country	US
Kind code	A1
Filing date	Jun 30, 2017
Priority date	Jun 30, 2017
Publication date	Jun 4, 2020
Grant date	—

Abstract

An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).

First claim

1 . An integrated circuit die comprising:
a device side and a backside opposite the device side, wherein the backside comprises at least one of a heat transfer enhancement configuration formed therein and a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface.

2 . The integrated circuit die of claim 1 , wherein the backside comprises a heat transfer enhancement configuration formed therein and the heat transfer enhancement configuration comprises a surface that has a greater surface area than a planar surface.

3 . The integrated circuit die of claim 2 , wherein the surface comprises a plurality of fins.

4 . The integrated circuit die of claim 1 , wherein the backside comprises a heat transfer enhancement structure that is a thermally conductive material.

5 . The integrated circuit die of claim 4 , wherein the thermally conductive material comprises a first surface coupled to the backside and an opposite second surface, wherein the second surface has a greater surface area than a planar surface.

6 . The integrated circuit die of claim 1 , wherein the heat transfer enhancement structure comprises a porous coating layer.

7 . The integrated circuit die of claim 6 , wherein the porous coating layer comprises a material that is functionalized to increase a hydrophilicity of the layer.

8 . The integrated circuit die of claim 6 , wherein the porous coating layer is a first structure and the heat transfer enhancement structure further comprises a second structure and the second structure comprises a thermally conductive material comprising a first surface coupled to the backside and an opposite second surface, wherein the second surface has a greater surface area than a planar surface.

9 . The integrated circuit die of claim 8 , wherein the porous coating layer comprises a material that is functionalized to increase a hydrophilicity of the layer.

10 . An integrated circuit assembly comprising:
an integrated circuit die coupled to a substrate, the integrated circuit die comprising a device side and a backside opposite the device side, wherein the backside comprises at least one of a heat transfer enhancement configuration formed therein and a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface; and a heat exchanger disposed partially or fully on the backside of the integrated circuit die.

11 . The integrated circuit assembly of claim 10 , wherein the heat exchanger comprises a fluid operable to directly impinge on the backside of the integrated circuit die.

12 . The integrated circuit assembly of claim 11 , wherein the backside of the integrated circuit die comprises a heat transfer enhancement configuration formed therein and the heat transfer enhancement configuration comprises a surface that has a greater surface area than a planar surface.

13 . The integrated circuit assembly of claim 11 , wherein the backside of the integrated circuit die comprises a heat transfer enhancement structure that is a thermally conductive material.

14 . The integrated circuit assembly of claim 13 , wherein the thermally conductive material comprises a first surface coupled to the backside of the integrated circuit die and an opposite second surface, wherein the second surface has a greater surface area than a planar surface.

15 . The integrated circuit assembly of claim 11 , wherein the backside of the integrated circuit die comprises a heat transfer enhancement structure that comprises a porous coating layer.

16 . The integrated circuit assembly of claim 15 , wherein the porous coating layer comprises a material that is functionalized to increase a hydrophilicity of the layer.

17 . The integrated circuit assembly of claim 15 , wherein the porous coating layer is a first structure and the heat transfer enhancement structure further comprises a second structure and the second structure comprises a thermally conductive material comprising a first surface coupled to the backside of the integrated circuit die and an opposite second surface, wherein the second surface has a greater surface area than a planar surface.

18 . The integrated circuit assembly of claim 10 , wherein the integrated circuit die is a first die, the integrated circuit assembly further comprising at least one second die, and wherein the heat exchanger is disposed partially or fully on the first die and the at least one second die.

19 . A method of forming an integrated circuit assembly comprising:
disposing a heat exchanger on a multi-chip package, the multi-chip package comprising at least one integrated circuit die comprising a device side and an opposite backside, wherein the backside comprises at least one of a heat transfer enhancement configuration formed therein and a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface; and contacting the backside of the at least one integrated circuit die with a fluid.

20 . The method of claim 19 , wherein the backside of the integrated circuit die comprises a heat transfer enhancement configuration formed therein and the heat transfer enhancement configuration comprises a surface that has a greater surface area than a planar surface.

21 . The method of claim 19 , wherein the backside of the at least one integrated circuit die comprises a heat transfer enhancement structure that comprises a first surface coupled to the backside and an opposite second surface, wherein the second surface has a greater surface area than a planar surface.

22 . The method of claim 19 , wherein the backside of the at least one integrated circuit die comprises a heat transfer enhancement structure that comprises a porous coating layer.

Assignees

• Intel Corp

Inventors

• Chang Je-Young
• Jha Chandra M
• Devasenathipathy Shankar
• Eid Feras
• Johnson John C

Classifications

• H01L23/4334

  Electricity · mapped topic

• H01L23/26

  Electricity · mapped topic

• F28D15/0275

  Arrangements for coupling heat-pipes together or with other structures, e.g. with base blocks; Heat pipe cores · CPC title

• H01L21/4882

  Electricity · mapped topic

• H01L23/3733

  Electricity · mapped topic