Printed circuit board

Patent metadata

Field	Value
Publication number	US-2020170110-A1
Application number	US-201916661051-A
Country	US
Kind code	A1
Filing date	Oct 23, 2019
Priority date	Nov 27, 2018
Publication date	May 28, 2020
Grant date	—

Abstract

A printed circuit board is provided. The printed circuit board includes an insulating material, and a circuit comprising a first region that partially penetrates the insulating material, and a second region formed on the first region and that protrudes from an upper portion of the insulating material, the first region includes a first electroplating layer and a first electroless plating layer that are formed between the insulating material and the first electroplating layer.

First claim

What is claimed is:

1 . A printed circuit board comprising:
an insulating material; and a circuit comprising a first region that partially penetrates the insulating material, and a second region formed on the first region and that protrudes from an upper portion of the insulating material, wherein the first region comprises a first electroplating layer and a first electroless plating layer that is formed between the insulating material and the first electroplating layer.

2 . The printed circuit board of claim 1 , wherein a width of the first region is larger than a width of the second region.

3 . The printed circuit board of claim 2 , wherein the second region comprises a second electroplating layer formed integrally with the first electroplating layer on an upper surface of the first electroplating layer.

4 . The printed circuit board of claim 3 , wherein a width of the second electroplating layer is smaller than a width of the first electroplating layer.

5 . The printed circuit board of claim 1 , wherein a width of the first region is smaller than a width of the second region.

6 . The printed circuit board of claim 5 , wherein the second region comprises
a second electroplating layer formed integrally with the first electroplating layer on an upper surface of the first electroplating layer, a metal foil disposed along a circumference of a part of an outer portion of the second electroplating layer, and formed on an upper surface of the insulating material, and a second electroless plating layer formed between the second electroplating layer and the metal foil, and further formed in an integral manner with the first electroless plating layer.

7 . The printed circuit board of claim 1 , wherein a width of the first region is the same as a width of the second region.

8 . The printed circuit board of claim 7 , wherein the second region comprises
a second electroplating layer formed in an integral manner with the first electroplating layer on an upper surface of the first electroplating layer, and a second electroless plating layer disposed along a circumference of a part of an outer portion of the second electroplating layer, and formed in an integral manner with the first electroless plating layer.

9 . The printed circuit board of claim 8 , wherein a height of the second electroplating layer is larger than a height of the second electroless plating layer.

10 . The printed circuit board of claim 1 , wherein a boundary surface between the first region and the insulating material is a concavely curved surface.

11 . The printed circuit board of claim 1 , further comprising:
a first pad formed in a lower surface of the insulating material; a via hole formed on the first pad, and configured to penetrate the insulating material; a via formed in the via hole; and a second pad formed on an upper surface of the via.

12 . The printed circuit board of claim 11 , wherein a thickness of the via is larger than a thickness of the first region, and a thickness of the second region is the same as a thickness of the second pad.

13 . The printed circuit board of claim 11 , wherein the first region is connected to the via, and the second region is connected to the second pad.

14 . The printed circuit board of claim 11 , wherein the via comprises a third electroless plating layer formed on an inner surface of the via hole and an upper surface of the first pad, and a third electroplating layer formed on the third electroless plating layer.

15 . The printed circuit board of claim 14 , wherein the second pad comprises
a fourth electroplating layer formed in an integral manner with the third electroplating layer on an upper surface of the third electroplating layer, a metal foil disposed along a circumference of a part of an outer portion of the third electroplating layer and further formed on an upper surface of the insulating material, and a fourth electroless plating layer formed between the third electroplating layer and the metal foil and further formed in an integral manner with the third electroless plating layer.

16 . The printed circuit board of claim 11 , wherein the via hole has a concavely curved surface.

17 . The printed circuit board of claim 11 , wherein the via hole penetrates an upper portion of the first pad.

18 . A method of manufacturing a printed circuit board, the method comprising:
forming a flexible insulating layer; and forming a circuit comprising a first region that partially penetrates the flexible insulating layer, and a second region formed on the first region and that protrudes from an upper portion of the flexible insulating layer, wherein the first region comprises a first electroplating layer and a first electroless plating layer that are formed between the flexible insulating layer and the first electroplating layer.

Assignees

• Samsung Electro Mech

Inventors

• Kang Seon-Ha
• Lee Sa-Yong
• Hwang Mi-Sun
• Kim Ju-Ho

Classifications

• H05K3/422

  characterised by electroless plating method; pretreatment therefor · CPC title

• H05K3/423

  characterised by electroplating method · CPC title

• H05K1/112

  directly combined with via connections · CPC title

• H05K1/118

  specially for flexible printed circuits, e.g. using folded portions · CPC title

• H05K1/115 Primary

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title