Manufacturing method for silicon nitride thin film, thin film transistor and display panel
US-2024153757-A1 · May 9, 2024 · US
Transistor and electronic device
US2020161469A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020161469-A1 |
| Application number | US-201816628610-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 31, 2018 |
| Priority date | Jul 12, 2017 |
| Publication date | May 21, 2020 |
| Grant date | — |
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Abstract
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[Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.
First claim
Opening claim text (preview).
1 . A transistor comprising: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer, a middle portion of a channel region of the semiconductor layer covered by the gate electrode being provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer. 2 . The transistor according to claim 1 , wherein the middle portion of the channel region of the semiconductor layer is provided in a shape in which the middle portion of the channel region of the semiconductor layer has a volume larger than a volume of one of the ends of the channel region of the semiconductor layer. 3 . The transistor according to claim 2 , wherein the middle portion of the channel region of the semiconductor layer is provided in a shape in which the middle portion of the channel region of the semiconductor layer has a width larger than a width of the at least one of the ends of the channel region of the semiconductor layer. 4 . The transistor according to claim 2 , wherein the middle portion of the channel region of the semiconductor layer is provided in a shape in which the middle portion of the channel region of the semiconductor layer has a taper larger than a taper of the at least one of the ends of the channel region of the semiconductor layer. 5 . The transistor according to claim 2 , wherein the middle portion of the channel region of the semiconductor layer is provided in a shape in which a height of the middle portion of the channel region of the semiconductor layer protruding from the semiconductor substrate is larger than a height of the at least one of the ends of the channel region of the semiconductor layer. 6 . The transistor according to claim 1 , wherein an ion impurity is introduced to the semiconductor layer, and polarity of an ion impurity introduced to the middle portion of the channel region of the semiconductor layer is different from polarity of an ion impurity introduced to an end of the channel region of the semiconductor layer. 7 . The transistor according to claim 1 , wherein the gate electrode is provided on the semiconductor layer via a gate insulating film provided on the semiconductor layer. 8 . The transistor according to claim 1 , wherein the semiconductor layer is provided by penetrating the insulating layer and protruding from the semiconductor substrate. 9 . The transistor according to claim 1 , wherein a source electrode or a drain electrode is coupled to the semiconductor layer protruding from the channel region. 10 . The transistor according to claim 9 , wherein at least one of ends provided in a shape different from a shape of the middle portion on the semiconductor layer comprises an end on a side to which the drain electrode is coupled. 11 . The transistor according to claim 1 , wherein the transistor is provided to a circuit included in a protection element. 12 . An electronic device comprising a circuit including a transistor including a semiconductor substrate, an insulating layer provided on the semiconductor substrate, a semiconductor layer provided on the insulating layer in a protruding manner, and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer, a middle portion of a channel region of the semiconductor layer covered by the gate electrode being provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.
Assignees
Inventors
Classifications
Electricity · mapped topic
- H01L29/786Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2020161469A1 cover?
- [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered b…
- Who is the assignee on this patent?
- Sony Semiconductor Solutions Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L29/786. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu May 21 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).