Top electrode interconnect structures

Patent metadata

Field	Value
Publication number	US-2020161236-A1
Application number	US-201816197646-A
Country	US
Kind code	A1
Filing date	Nov 21, 2018
Priority date	Nov 21, 2018
Publication date	May 21, 2020
Grant date	—

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.

First claim

1 . A structure, comprising:
a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature wherein the structure is a memory device.

2 . (canceled)

3 . The structure of claim 1 , wherein the memory device is a RRAM (Resistive RAM), PRAM (Phase-change RAM), or MRAM (Magnetic RAM).

4 . The structure of claim 1 , further comprising a periphery device or logic device comprising the lower metallization feature and the upper metallization feature connected together by an interconnect structure devoid of any intervening materials.

5 . The structure of claim 1 , wherein the self-aligned via interconnection is in a self-forming self-aligned via which exposes the top electrode.

6 . The structure of claim 5 , further comprising a spacer material defining the self-forming self-aligned via and surrounding the self-aligned via interconnection.

7 . The structure of claim 5 , further comprising a liner material defining the self-forming self-aligned via and surrounding the top electrode, the one or more switching material, the bottom electrode and the self-aligned via interconnection.

8 . The structure of claim 7 , further comprising a spacer material on an inner side of the liner material, which defines the self-forming self-aligned via and surrounding the self-aligned via interconnection.

9 . The structure of claim 1 , wherein the top electrode is formed from one or more of conductive materials including: TiN, TaN, WN, Al, Ru, Ir, Pt, Ag, Au, Co, W, Cu or their combination of multi-layer films.

10 . The structure of claim 1 , wherein the bottom electrode, the one or more switching materials, the top electrode and the self-aligned via interconnection have vertically aligned sidewalls forming a vertical pillar structure.

11 . A structure, comprising:
a memory device comprising:
a first metallization layer;
a second metallization layer; and
a vertical pillar connecting the first metallization layer to the second metallization layer, the vertical pillar including an aligned via interconnection in contact with a top electrode of the vertical pillar and the second metallization layer; and
a periphery device or logic device comprising the lower metallization feature and the upper metallization feature connected together by an interconnect structure devoid of the aligned via interconnection and the vertical pillar wherein the vertical pillar and the aligned via interconnection have vertically aligned sidewalls forming a vertical pillar structure.

12 . The structure of claim 11 , wherein the memory device is a RRAM (Resistive RAM), PRAM (Phase-change RAM), or MRAM (Magnetic RAM).

13 . The structure of claim 24 , wherein the self-aligned via interconnection is in a self-forming self-aligned via which exposes the top electrode.

14 . The structure of claim 13 , further comprising a spacer material defining the self-forming self-aligned via and surrounding the self-aligned via interconnection.

15 . The structure of claim 13 , wherein the vertical pillar has a narrower cross-section at the self-forming self-aligned via the top electrode.

16 . The structure of claim 14 , further comprising a liner material defining the self-forming self-aligned via and surrounding the vertical pillar and the self-aligned via interconnection.

17 . (canceled)

18 . (canceled)

19 . (canceled)

20 . (canceled)

21 . A structure, comprising:
a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a via interconnection in contact with the top electrode and the upper metallization feature, wherein the bottom electrode, the one or more switching materials, the top electrode and the via interconnection have vertically aligned sidewalls forming a vertical pillar structure.

22 . The structure of claim 21 , wherein the via interconnection is a self-aligned via interconnection.

23 . The structure of claim 21 , further comprising a periphery device or logic device comprising the lower metallization feature and the upper metallization feature connected together by an interconnect structure devoid of any intervening materials.

24 . The structure of claim 13 , wherein the aligned via interconnection is a self-aligned via interconnection.

Assignees

• Globalfoundries Inc

Inventors

• Kim Il Goo
• Augur Roderick A

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H01L21/76897

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L23/5226 Primary

  Electricity · mapped topic