Ferroelectric field effect transistors (fefets) having ambipolar channels

Patent metadata

Field	Value
Publication number	US-2020144293-A1
Application number	US-201716630839-A
Country	US
Kind code	A1
Filing date	Sep 12, 2017
Priority date	Sep 12, 2017
Publication date	May 7, 2020
Grant date	—

Abstract

Ferroelectric field effect transistors (FeFETs) having ambipolar channels are described. In an example, an integrated circuit structure includes a channel layer above a substrate. The channel layer is composed of an ambipolar material. A ferroelectric oxide material is above the channel layer. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a channel layer above a substrate, the channel layer comprising an ambipolar material; a ferroelectric oxide material above the channel layer; a gate electrode on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side; a first source/drain region at the first side of the gate electrode; and a second source/drain region at the second side of the gate electrode.

2 . The integrated circuit structure of claim 1 , wherein the ambipolar material is selected from the group consisting of graphene, silicone, tungsten selenide (WSe2) and phosphorine.

3 . The integrated circuit structure of claim 1 , wherein the ambipolar material is an amorphous or a polycrystalline ambipolar material.

4 . The integrated circuit structure of claim 1 , wherein the ferroelectric oxide material is selected from the group consisting of lead zirconate titanate (PZT), strontium bismuth tantalum oxide (SBT), and lanthanum-doped lead zirconium titanate (PLZT).

5 . The integrated circuit structure of claim 1 , wherein the ferroelectric oxide material comprises hafnium and oxygen.

6 . The integrated circuit structure of claim 1 , further comprising:
an insulator material layer between and in contact with the ferroelectric oxide material and the channel layer.

7 . The integrated circuit structure of claim 1 , wherein the integrated circuit structure is a two-state memory cell.

8 . The integrated circuit structure of claim 1 , further comprising:
a non-volatile memory cell coupled to the second source/drain region, the non-volatile memory cell selected from the group consisting of a spin torque transfer random access memory (STTRAM) cell, a resistive random access memory (RRAM) cell, and a conductive bridge random access memory (CBRAM) cell.

9 . An integrated circuit structure, comprising:
a semiconductor fin above a substrate, the semiconductor fin having a top and sidewalls, and the semiconductor fin comprising an ambipolar material; a ferroelectric oxide material above the top and laterally adjacent to the sidewalls of the semiconductor fin; a gate electrode on the ferroelectric oxide material above the top and laterally adjacent to the sidewalls of the semiconductor fin, the gate electrode having a first side and a second side opposite the first side; a first source/drain region at the first side of the gate electrode; and a second source/drain region at the second side of the gate electrode.

10 . The integrated circuit structure of claim 9 , wherein the ambipolar material is selected from the group consisting of graphene, silicone, tungsten selenide (WSe2) and phosphorine.

11 . The integrated circuit structure of claim 9 , wherein the ambipolar material is an amorphous or a polycrystalline ambipolar material.

12 . The integrated circuit structure of claim 9 , wherein the ferroelectric oxide material is selected from the group consisting of lead zirconate titanate (PZT), strontium bismuth tantalum oxide (SBT), and lanthanum-doped lead zirconium titanate (PLZT).

13 . The integrated circuit structure of claim 9 , wherein the ferroelectric oxide material comprises hafnium and oxygen.

14 . The integrated circuit structure of claim 9 , further comprising:
an insulator material layer between and in contact with the ferroelectric oxide material and the semiconductor fin.

15 . The integrated circuit structure of claim 9 , wherein the integrated circuit structure is a two-state memory cell.

16 . The integrated circuit structure of claim 9 , further comprising:
a non-volatile memory cell coupled to the second source/drain region, the non-volatile memory cell selected from the group consisting of a spin torque transfer random access memory (STTRAM) cell, a resistive random access memory (RRAM) cell, and a conductive bridge random access memory (CBRAM) cell.

17 . An integrated circuit structure, comprising:
a semiconductor nanowire above a substrate, the semiconductor nanowire having a top, a bottom and sidewalls, and the semiconductor nanowire comprising an ambipolar material; a ferroelectric oxide material above the top, below the bottom, and laterally adjacent to the sidewalls of the semiconductor nanowire; a gate electrode on the ferroelectric oxide material above the top, below the bottom and laterally adjacent to the sidewalls of the semiconductor nanowire, the gate electrode having a first side and a second side opposite the first side; a first source/drain region at the first side of the gate electrode; and a second source/drain region at the second side of the gate electrode.

18 . The integrated circuit structure of claim 17 , wherein the ambipolar material is selected from the group consisting of graphene, silicone, tungsten selenide (WSe2) and phosphorine.

19 . The integrated circuit structure of claim 17 , wherein the ambipolar material is an amorphous or a polycrystalline ambipolar material.

20 . The integrated circuit structure of claim 17 , wherein the ferroelectric oxide material is selected from the group consisting of lead zirconate titanate (PZT), strontium bismuth tantalum oxide (SBT), and lanthanum-doped lead zirconium titanate (PLZT).

21 . The integrated circuit structure of claim 17 , wherein the ferroelectric oxide material comprises hafnium and oxygen.

22 . The integrated circuit structure of claim 17 , further comprising:
an insulator material layer between and in contact with the ferroelectric oxide material and the semiconductor nanowire.

23 . The integrated circuit structure of claim 17 , wherein the integrated circuit structure is a two-state memory cell.

24 . The integrated circuit structure of claim 17 , further comprising:
a non-volatile memory cell coupled to the second source/drain region, the non-volatile memory cell selected from the group consisting of a spin torque transfer random access memory (STTRAM) cell, a resistive random access memory (RRAM) cell, and a conductive bridge random access memory (CBRAM) cell.

Assignees

• Intel Corp

Inventors

• Majhi Prashant
• Doyle Brian S
• Karpov Elijah V
• Sharma Abhishek A
• Pillarisetty Ravi

Classifications

• H01L29/78391

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic

• H01L27/2454

  Electricity · mapped topic

• H01L27/11585 Primary

  Electricity · mapped topic

• H10D62/80

  characterised by the materials · CPC title