Method of fabricating integrated circuits

Patent metadata

Field	Value
Publication number	US-2020135490-A1
Application number	US-201916601358-A
Country	US
Kind code	A1
Filing date	Oct 14, 2019
Priority date	Oct 25, 2018
Publication date	Apr 30, 2020
Grant date	—

Abstract

A method of fabricating an integrated circuit is disclosed. The method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process comprises the steps of: plasma etching an excess metal portion of the metal interconnection layer using plasma comprising a noble gas, for an etch duration. The method further comprises stopping the etch process prior to the excess metal portion being completely removed and thus prior to a dielectric surface upon which the metal interconnection is formed, becoming completely exposed. The remaining excess metal portion comprising excess metal residues is subsequently removed using a second etch step.

First claim

What is claimed is:

1 . A method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process, the metal interconnection layer being disposed between a dielectric layer and an integrated circuit, the method comprising the steps of:
plasma etching an excess metal portion of the metal interconnection layer for an etch duration, using a plasma comprising a noble gas, the excess metal portion being disposed on a surface of the dielectric layer; controlling the etch duration so as to stop the plasma etching before the excess metal portion is completely removed from the dielectric layer; etching the remaining excess metal portion to remove excess metal residues from the dielectric layer.

2 . A method according to claim 1 , wherein the noble gas comprises argon.

3 . A method according to claim 1 , wherein the etching of the remaining excess metal portion comprises wet chemical etching.

4 . A method according to claim 1 , wherein the etching of the remaining excess metal portion comprises chemical dry etching.

5 . A method according to claim 4 , wherein the chemical dry etching comprises etching using a fluorocarbon.

6 . A method according to claim 5 , wherein the fluorocarbon comprises tetrafluoromethane.

7 . A method according to claim 5 , wherein the chemical dry etching comprises etching using chlorine.

8 . A method according to claim 1 , wherein the excess metal portion comprises a barrier layer or layers disposed on the dielectric layer and a copper layer disposed on the barrier layer(s).

9 . A method according to claim 8 , wherein the excess metal residues comprise barrier layer residues.

10 . A method according to claim 1 , further comprising dynamically calculating the etch duration during the etch process.

11 . A method according to claim 10 , wherein the etch duration is set when the surface of the dielectric layer is detected during the plasma etching.

12 . A method according to claim 10 , wherein the surface of the dielectric layer is detected using optical emission spectroscopy (OES) or secondary ion mass spectroscopy (SIMS).

13 . A method according to claim 1 , further comprising calculating the etch duration prior to plasma etching, wherein the etch duration is calculated based on a known etch rate of the excess metal portion.

14 . A method according to claim 1 , wherein the step of plasma etching the excess metal portion comprises preferentially etching the excess metal portion along a direction substantially transverse to the metal interconnection layer.

15 . An integrated circuit obtainable by a method according to claim 1 .

Assignees

• Spts Technologies Ltd

Inventors

• Wilby Tony
• Burgess Steve

Classifications

• H01J37/32926

  Software, data control or modelling · CPC title

• H01J37/32972

  Spectral analysis · CPC title

• H01L21/76895

  Electricity · mapped topic

• H01L21/32134

  Electricity · mapped topic

• H01L21/32136 Primary

  Electricity · mapped topic