Memory transaction request management

Patent metadata

Field	Value
Publication number	US-2020133730-A1
Application number	US-201916592074-A
Country	US
Kind code	A1
Filing date	Oct 3, 2019
Priority date	Oct 31, 2018
Publication date	Apr 30, 2020
Grant date	—

Abstract

A method of requesting data items from storage. The method comprising allocating each of a plurality of memory controllers a unique identifier and assigning memory transaction requests for accessing data items to a memory controller according to the unique identifiers. The data items are spatially local to one another in storage. The data items are requested from the storage via the memory controllers according to the memory transaction requests and then buffered if the data items are received out of order relative to an order in which the data items are requested

First claim

What is claimed is:

1 . A method of requesting data items from storage, the method comprising:
allocating each of a plurality of memory controllers a unique identifier; assigning memory transaction requests for accessing data items to a memory controller according to the unique identifiers, wherein the data items are spatially local to one another in storage; requesting the data items from the storage via the memory controllers according to the memory transaction requests; and buffering the requested data items if the data items are received out of order relative to an order in which the data items are requested.

2 . The method of requesting data items from storage according to claim 1 , wherein the spatially local data items have substantially sequential memory access addresses.

3 . The method of requesting data items from storage according to claim 1 , further comprising the step of ordering the transaction requests across the plurality of memory controllers to reduce the amount of buffering required.

4 . The method of requesting data items from storage according to claim 1 , wherein the storage is any of random-access memory, dynamic-random access memory, or non-volatile memory.

5 . The method of requesting data items from storage according to claim 1 , wherein the memory controllers are dynamic memory access controllers.

6 . A processor comprising:
an allocation module for allocating each of a plurality of memory controllers a unique identifier; an assignment module for assigning memory transaction requests issued by the processor to one of the memory controllers according to the unique identifier allocated to the memory controller, wherein the memory transaction requests each represent a request for a respective data item in a plurality of data items that are spatially local to one another in storage; and a buffer for storing data item requested by the memory controllers if the data items are received out of order relative to an order in which the data items are requested.

7 . The processor of claim 6 , wherein the spatially local data items have substantially sequential memory access addresses.

8 . The processor of claim 6 , further comprising an ordering module for ordering the memory transaction requests across the plurality of memory controllers so as to minimise the amount of data items in the buffer.

9 . The processor of claim 6 , wherein the storage is any of random-access memory, dynamic-random access memory, or non-volatile memory.

10 . The processor of claim 6 , wherein the memory controllers are dynamic memory access controllers.

11 . The processor of claim 6 , wherein the processor is a machine learning processor.

12 . A transaction management system comprising:
storage; a plurality of memory controllers arranged to access the storage; and a processor for allocating memory transaction requests to each of the plurality of memory controllers for data items that are spatially local to one another in the storage.

13 . The transaction management system of claim 12 , wherein the storage is any of random-access memory, dynamic-random access memory, or non-volatile memory.

14 . The transaction management system of claim 12 , wherein the memory controllers are dynamic memory access controllers.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Ingram Graeme Leslie

Classifications

• G06F13/1673 Primary

  using buffers · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F13/1626

  by reordering requests · CPC title

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title