Method for accessing extended memory, device, and system

Patent metadata

Field	Value
Publication number	US-10545672-B2
Application number	US-201715788990-A
Country	US
Kind code	B2
Filing date	Oct 20, 2017
Priority date	Apr 23, 2015
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

First claim

What is claimed is:

1. A method performed by an extended memory controller for accessing an extended memory of a computer, the method comprising:
receiving, from a processor system of the computer, a first memory access request for reading requested data stored in the extended memory, wherein the first memory access request comprises a first access address of the requested data;
sending to the extended memory a read request for reading the requested data, wherein the read request comprises a physical address of the requested data corresponding to the first access address;
sending, to the processor system in response to the first memory access request and before the requested data is received from the extended memory, a first response message indicating that the extended memory controller has not obtained the requested data;
receiving, after sending the first response message, the requested data from the extended memory;
writing the requested data into a data buffer of the extended memory controller;
receiving a second memory access request from the processor system after receiving the first memory access request, wherein the second memory access request comprises a second access address;
determining that the second access address also corresponding to the physical address of the requested data, wherein the second access address is different from the first access address;
sending the requested data in the data buffer to the processor system in response to the second memory access request.

2. The method according to claim 1 , further comprising:
receiving, from the processor system, a third memory access request comprising a third access address before receiving the requested data from the extended memory, wherein the third access address is different from the first access address and the second access address, and the third access address also corresponds to the physical address;
sending, to the processor system in response to the third memory access request, a third response message indicating the data has not been obtained.

3. The method according to claim 1 , wherein the first access address comprises a first bank address and a first row address, the second access address comprises the first bank address and a second row address, and wherein the first row address is different from the second row address.

4. The method according to claim 1 , further comprising:
creating, a record in the data buffer, wherein the record comprises a tag field and a validity field, wherein the tag field corresponds to the physical address, and wherein the validity field indicates invalidity before receiving the data from the extended memory.

5. The method according to claim 4 , further comprising:
storing the requested data received from the extended memory in a data field of the record; and
setting the validity field of the record to indicate validity.

6. A method performed by a processor system of a computer for accessing an extended memory of the computer via an extended memory controller of the computer, the method comprising:
receiving a storage address of requested a data stored in the extended memory;
generating according to the storage address of the requested data, N+1 memory access requests each containing an access address, wherein the access addresses of the N+1 memory access requests are different from each other and correspond to a same physical address of the requested data in the extended memory, N≥1, and N being an integer; and
sending the N+1 memory access requests to the extended memory controller.

7. The method according to claim 6 , further comprising determining N according to a delay parameter for obtaining the requested data from the extended memory by the computer, wherein the delay parameter comprises:
a delay tPD1 of transmitting a memory access request from the extended memory controller to the extended memory;
a delay tPD2 of transmitting the data accessed by the memory access request, from the extended memory to the extended memory controller; or
a time interval T_Interval between two consecutive memory access requests sent by the processor system.

8. The method according to claim 7 , wherein N is no less than a rounding of (tPD1+tPD2)/T_Interval.

9. The method according to claim 7 , wherein a value of the T_Interval corresponds to tGAP min =tRCD+tRTP+tRP, the tRCD indicating a minimum time interval from sending an activate command to sending the read command, tRTP indicating a minimum time interval from sending the read command to sending a pre-charge command, and tRP indicating a minimum time interval from sending the pre-charge command to sending a next activate command.

10. The method according to claim 7 , wherein a value of the T_Interval corresponds to a delay for executing, by the processor system, a fence instruction between two consecutive memory access requests.

11. The method according to claim 6 , wherein:
N access addresses of N of the N+1 memory access requests are generated according to a physical address that is converted from the storage address of the data, wherein the storage address is a virtual address, wherein the N access addresses include distinct row addresses for pointing to the same physical address, each distinct row address based on different multiples of a quantity of memory rows in the extended memory in combination with a row address of the physical address, and wherein each of the N access addresses comprises a same bank address of the physical address and a different row address of the physical address to cause a row miss in the processor system.

12. An extended memory system, comprising:
an extended memory;
an extended memory controller coupled to the extended memory;
the extended memory controller being configured to:
receive, from a processor system of a computer, a first memory access request for reading requested data stored in the extended memory, wherein the first memory access request comprises a first access address of the requested data;
send, to the extended memory, a read request for reading the requested data, wherein the read request comprises a physical address of the requested data corresponding to the first access address;
send, to the processor system in response to the first memory access request and before the requested data is received from the extended memory, a first response message indicating the requested data has not been obtained by the extended memory controller;
receive the requested data from the extended memory after sending the first response message;
write the requested data into a data buffer of the extended memory controller;
receive, from the processor system after receiving the first memory access request, a second memory access request comprising a second access address;
determine that the second access address also corresponds to the physical address of the requested data, wherein the second access address is different from the first access address;
send the requested data in the data buffer to the processor system in response to the second memory access request.

13. The extended memory system according to claim 12 , wherein the extended memory controller is further configured to:
receive, from the processor system, a third memory access request comprising a third access address before receiving the data from the extended memory, wherein the third access address is different from the first access address and the second access address, and the third access address also corresponds to the physical address of the requested data;
send, to the processor system in response to the third memory access request, a third response message indicat

Assignees

• Huawei Tech Co Ltd

Inventors

• Cui Zehan
• Chen Mingyu
• Liu Yao
• Ruan Yuan

Classifications

• G06F2213/0064

  Latency reduction in handling transfers · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0859

  with reload from main memory · CPC title

• G06F12/0623

  for memory modules · CPC title