Integrated circuits and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-2020126986-A1
Application number	US-201916723939-A
Country	US
Kind code	A1
Filing date	Dec 20, 2019
Priority date	May 26, 2010
Publication date	Apr 23, 2020
Grant date	—

Abstract

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area on a substrate having a top surface; a second diffusion area for a second type transistor, the second type transistor including a second drain region and a second source region in the second diffusion area; an isolation structure interposing the first and second diffusion areas; a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction; a first metallic structure extending in the routing direction, the first metallic structure overlaps the first diffusion area in the routing direction for a first distance (D1); a second metallic structure extending in the routing direction and disposed collinear with the first metallic structure, wherein the second metallic structure overlaps the second diffusion area in the routing direction for a third distance (D3); a third metallic structure extending in to the routing direction and extending a second distance (D2) over the first diffusion area, extending over the isolation structure, and extending a fourth distance (D4) over the second diffusion area; wherein the first and second metallic structures are coupled to the first and second source regions and the third metallic structure is coupled to the first and second drain regions.

2 . The integrated circuit of claim 1 , wherein D1 plus D2 is substantially equal to a first width of the first diffusion area in the routing direction.

3 . The integrated circuit of claim 3 , wherein D3 plus D4 is substantially equal to a second width of the second diffusion area in the routing direction.

4 . The integrated circuit of claim 1 , wherein D2 is greater than D1 and D3 is greater than D4.

5 . The integrated circuit of claim 1 , further comprising:
a fourth metallic structure under the first metallic structure and directly interfacing the first source region; a fifth metallic structure under the second metallic structure and directly interfacing the second source region.

6 . The integrated circuit of claim 5 , wherein a width of the fourth metallic structure in a direction perpendicular the routing direction is equal to a width of the first metallic structure in the direction.

7 . The integrated circuit of claim 6 , wherein a width of the fifth metallic structure in the direction perpendicular the routing direction is equal to a width of the second metallic structure in the direction.

8 . The integrated circuit of claim 5 , wherein the fourth metallic structure is a different composition than the first metallic structure and the fifth metallic structure is a different composition that the second metallic structure.

9 . The integrated circuit of claim 5 , wherein the fourth metallic structure is tungsten and the first metallic structure is copper.

10 . An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area on a substrate having a top surface; a second diffusion area for a second type transistor, the second type transistor including a second drain region and a second source region in the second diffusion area; an isolation structure interposing the first and second diffusion areas; a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction; a first copper structure extending in the routing direction, the first copper structure overlaps the first diffusion area in the routing direction for a first distance (D1); a second copper structure extending in the routing direction and disposed collinear with the first copper structure, wherein the second copper structure overlaps the second diffusion area in the routing direction for a third distance (D3); a third copper structure extending in to the routing direction and having a first portion extending a second distance (D2) over the first diffusion area and a third portion extending a fourth distance (D4) over the second diffusion area, wherein a second portion of the third copper structure extends between the first and third portions, the second portion interfaces a top surface of the isolation structure; a first tungsten structure underlie the first portion of the third copper structure and interfacing the first drain region; a second tungsten structure underlying the third portion of the third copper structure and interfacing the second drain region.

11 . The integrated circuit of claim 10 , wherein the second portion of the third copper structure interfaces sidewalls of each of the first tungsten structure and the second tungsten structure.

12 . The integrated circuit of claim 10 , wherein a top surface of each of the first, second and third portions of the third copper structure are coplanar.

13 . The integrated circuit of claim 12 , wherein the top surface of each of the first, second and third portions of the third copper structure is coplanar with a top surface of the first copper structure and the second copper structure.

14 . The integrated circuit of claim 10 , further comprising:
a fourth tungsten structure interfacing the first source region and the first copper structure; and a fifth tungsten structure interfacing the second source region and the second copper structure.

15 . The integrated circuit of claim 10 , wherein D1 plus D2 is substantially equal to a first width of the first diffusion area in the routing direction.

16 . The integrated circuit of claim 15 , wherein the D3 plus D4 is substantially equal to a second width of the second diffusion area in the routing direction

17 . An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area; a second diffusion area for a second type transistor, the second diffusion area being separated from the first diffusion area, the second type transistor including a second drain region and a second source region in the second diffusion area, the first diffusion area and the second diffusion area formed in a substrate; a gate structure including a gate electrode continuously extending across the first diffusion area between the first drain region and the first source region and across the second diffusion area between the second drain region and the second source region, the extending of the gate structure being in a routing direction, wherein the gate structure further includes an interfacial layer disposed below the gate electrode, the interfacial layer physically interfacing a top surface of the substrate; a first metallic structure of tungsten disposed on and physically interfacing a silicide region of the first source region, wherein the first metallic structure overlaps a first distance of the first diffusion area in the routing direction, wherein the first metallic structure includes a first top surface, wherein the first source region including the silicide region of the first source region extends above the top surface the substrate; a second metallic structure of tungsten disposed on and physically interfacing a silicide region of the second source region, wherein the second metallic structure overlaps a second distance of the second diffusion area in the routing direction, wherein the second metallic structure includ

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Keshavarzi Ali
• Guo Ta-Pen
• Sung Shu-Hui
• Tseng Hsiang-Jen
• Lin Shyue-Shyh
• Lu Lee-Chung
• Wu Chung-Cheng
• Tien Li-Chun
• Yang Jung-Chan
• Chen Ting-Yu
• Cao Min
• Hou Yung-Chin

Classifications

• H01L29/495

  Electricity · mapped topic

• H01L21/823871

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L29/7833

  Electricity · mapped topic

• H01L29/4238

  Electricity · mapped topic