Skip via for metal interconnects

Patent metadata

Field	Value
Publication number	US-2020111736-A1
Application number	US-201816153901-A
Country	US
Kind code	A1
Filing date	Oct 8, 2018
Priority date	Oct 8, 2018
Publication date	Apr 9, 2020
Grant date	—

Abstract

Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.

First claim

1 . A method of forming a skip via structure in a semiconductor device, the method comprising:
forming a first metallization level (Mx) on a substrate comprising depositing a first interlayer dielectric including one or more semiconductor devices, forming at least one first metal conductor in the first dielectric layer, wherein the at least one metal conductor and the first dielectric have coplanar surfaces, and depositing a first cap layer on the coplanar surfaces; forming a second metallization level (Mx+1) on the first metallization level (Mx) comprising depositing a second interlayer dielectric on the first cap layer and filling the openings in the first cap layer, forming at least one second metal conductor in the second dielectric layer, wherein the second metal conductor comprises a second cap layer on a top surface thereof and a liner layer that collectively encapsulates the second metal conductor; patterning the second cap layer to form openings corresponding to the location of the skip via structure; forming a third interconnect level (Mx+2) on the second metallization level (Mx+1) comprising depositing a third interlayer dielectric and filling the openings in the second cap layer with the third interlayer dielectric; forming a via opening at the location of the skip via structure in the second and third dielectric layers to the first metal conductor; and filling the via opening with a metal conductor, wherein the second metal conductor in the second interconnect level is electrically isolated from the filled via opening extending from the third interconnect level to the first metal conductor of the first interconnect level, and wherein the second and third interlayer dielectrics have substantially the same etch selectivities.

2 . The method of claim 1 , wherein the first, second and third interlayer dielectrics comprise different materials.

3 . The method of claim 1 , wherein filling the via opening with the metal conductor comprises depositing a barrier layer on the sidewalls defining the via opening prior to filling the via opening with the metal conductor.

4 . The method of claim 1 , wherein the interlayer dielectric comprises SiO 2 , silsesquioxanes, carbon doped oxides that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof.

5 . The method of claim 1 , wherein the first and second cap layers comprise tantalum, tantalum nitride, cobalt, ruthenium, titanium, titanium nitride, tungsten nitride, or combinations thereof.

6 . The method of claim 1 , wherein the first and second cap layers comprise silicon nitride, a silicon oxynitride, a silicon carbonitride, a silicon boronitride, a silicon borocarbide, a silicon borocarbonitride, a boron carbide, a boron nitride, silicon oxycarbide, hydrogenated silicon carbide, silicon dioxide, organosilicate glass, or combinations thereof

7 . The method of claim 1 further comprising planarizing the first and second interlayer dielectrics prior to depositing the first and second cap layer, respectively, to provide planar top surfaces.

8 . A method of forming a skip via structure in a semiconductor device, the method comprising:
forming a first metallization level (Mx) on a substrate comprising depositing a first interlayer dielectric including one or more semiconductor devices, forming at least one first metal conductor in the first dielectric layer, wherein the at least one first metal conductor and the first dielectric have coplanar surfaces, and depositing a first cap layer on the coplanar surfaces; forming a second metallization level (Mx+1) on the first metallization level (Mx) comprising depositing a second interlayer dielectric on the first cap layer, forming at least one second metal conductor in the second dielectric layer, forming a sacrificial layer on the second interlayer dielectric, patterning the sacrificial layer, depositing a second cap layer, and removing the sacrificial layer pattern to form openings in the second cap layer corresponding to a location of the skip via structure; forming a third interconnect level (Mx+2) on the second metallization level (Mx+1) comprising depositing a third interlayer dielectric and filling the openings in the second cap layer with the third interlayer dielectric; forming a skip via opening at the location of the skip via structure in the second and third dielectric layers to the first metal conductor; and filling the skip via opening with a metal conductor, wherein the second metal conductor in the second interconnect level is electrically isolated from the metal conductor filled via opening extending from the third interconnect level to the first metal conductor of the first interconnect level, and wherein the second and third interlayer dielectrics have substantially the same etch selectivities.

9 . The method of claim 8 , wherein the first, second and third interlayer dielectrics comprise different materials.

10 . The method of claim 8 , wherein filling the skip via opening with the metal conductor comprises depositing a barrier layer on surfaces defining the via opening prior to filling the via opening with the metal conductor.

11 . The method of claim 8 , wherein the first, second and third interlayer dielectrics comprise SiO 2 , silsesquioxanes, carbon doped oxides that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof.

12 . The method of claim 8 , wherein the first and second cap layers comprise tantalum, tantalum nitride, cobalt, ruthenium, titanium, titanium nitride, tungsten nitride, or combinations thereof.

13 . The method of claim 8 , wherein the first and second cap layers comprise silicon nitride, a silicon oxynitride, a silicon carbonitride, a silicon boronitride, a silicon borocarbide, a silicon borocarbonitride, a boron carbide, a boron nitride, silicon oxycarbide, hydrogenated silicon carbide, silicon dioxide, organosilicate glass, or combinations thereof

14 . The method of claim 8 further comprising planarizing the third interlayer dielectric subsequent to depositing the third interlayer dielectric to provide a planar top surface.

15 - 20 . (canceled)

Assignees

• IBM

Inventors

• Amanapu Hari Prasad
• Bhosale Prasad
• Licausi Nicholas V
• Liebmann Lars W
• Mcmahon James J
• Peethala Cornelius Brown
• Rizzolo Michael

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H01L21/76843

  Electricity · mapped topic

• H01L21/76816

  Electricity · mapped topic

• H01L23/5226 Primary

  Electricity · mapped topic

• H01L21/76829

  Electricity · mapped topic