Thin-film transistors with vertical channels

Patent metadata

Field	Value
Publication number	US-2020105892-A1
Application number	US-201816146654-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate oriented in a horizontal direction; a transistor above the substrate, wherein the transistor includes:
a source electrode above the substrate, oriented in the horizontal direction;
a channel layer including a channel material above and in contact with a portion of the source electrode, the channel layer oriented in a vertical direction substantially orthogonal to the horizontal direction;
a gate dielectric layer above the source electrode and the channel layer, conformingly covering a top surface of the source electrode and surfaces of the channel layer;
a gate electrode above a portion of the channel layer, conformingly covering a portion of the gate dielectric layer, and separated from the channel layer by the gate dielectric layer; and
a drain electrode above and in contact with the channel layer, oriented in the horizontal direction, wherein a current path is to include a vertical current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a horizontal current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode.

2 . The semiconductor device of claim 1 , wherein the channel layer is of a rectangular prism shape, and the gate electrode includes a horizontal portion above a top surface of the channel layer, and two vertical portions along sidewalls of the channel layer.

3 . The semiconductor device of claim 1 , wherein the drain electrode is separated from the gate electrode by a spacer between the drain electrode and the gate electrode.

4 . The semiconductor device of claim 1 , wherein the drain electrode is a first drain electrode, and the transistor further includes a second drain electrode above and in contact with the channel layer, oriented in the horizontal direction, wherein the current path is to include the vertical current portion from the source electrode along the gated region of the channel layer under the gate electrode in the vertical direction, a first horizontal current portion along a first ungated region of the channel layer in the horizontal direction from the gate electrode to the first drain electrode, and a second horizontal current portion along a second ungated region of the channel layer in the horizontal direction from the gate electrode to the second drain electrode.

5 . The semiconductor device of claim 1 , wherein the drain electrode has a first length and a first width, the source electrode has a second length and a second width, the second length is different from the first length, or the second width is different from the first width.

6 . The semiconductor device of claim 1 , wherein the drain electrode includes a first conductive material, and the source electrode includes a second conductive material different from the first conductive material.

7 . The semiconductor device of claim 1 , wherein the source electrode is coupled to a first metal electrode located in a first metal layer, the drain electrode is coupled to a second metal electrode located in a second metal layer, and the second metal layer is separated from the first metal layer by an inter-level dielectric (ILD) layer.

8 . The semiconductor device of claim 7 , wherein the source electrode is coupled by a first short via to the first metal electrode located in the first metal layer, or the drain electrode is coupled by a second short via to the second metal electrode located in the second metal layer.

9 . The semiconductor device of claim 1 , wherein the gate electrode, the channel layer, the source electrode, and the drain electrode are within an ILD layer above the substrate.

10 . The semiconductor device of claim 9 , wherein the ILD layer includes a material selected from the group consisting of silicon dioxide (SiO 2 ), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, and organosilicate glass.

11 . The semiconductor device of claim 1 , wherein the gate dielectric layer includes a high-K dielectric material selected from the group consisting of hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, aluminum oxide, and nitride hafnium silicate.

12 . The semiconductor device of claim 1 , wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate.

13 . The semiconductor device of claim 1 , wherein the gate electrode, the source electrode, or the drain electrode includes a material selected from the group consisting of titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), and an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, Ru, TiAlN, HfAlN, or InAlO.

14 . The semiconductor device of claim 1 , wherein the channel layer includes a material selected from the group consisting of CuS 2 , CuSe 2 , WSe 2 , MoS 2 , MoSe 2 , WS 2 , indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si 2 BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC), molybdenum and sulfur, and a group-VI transition metal dichalcogenide.

15 . A method for forming a vertical thin film transistor (TFT), the method comprising:
forming a source electrode above a substrate, oriented in a horizontal direction, wherein the substrate is oriented in the horizontal direction; forming a channel layer including a channel material above and in contact with a portion of the source electrode, the channel layer oriented in a vertical direction substantially orthogonal to the horizontal direction; forming a gate dielectric layer above the source electrode and the channel layer, conformingly covering a top surface of the source electrode and surfaces of the channel layer; forming a gate electrode above a portion of the channel layer, conformingly covering a portion of the gate dielectric layer, and separated from the channel layer by the gate dielectric layer; and forming a drain electrode above and in contact with the channel layer, oriented in the horizontal direction, wherein a current path is to include a vertical current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a horizontal current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode.

16 . The method of claim 15 , further comprising:
forming a spacer between the drain electrode and the gate electrode to separate the drain electrode from the gate electrode.

17 . The method of claim 15 , wherein the drain electrode is a first drain electrode, and the method

Assignees

• Intel Corp

Inventors

• Haratipour Nazila
• Ghani Tahir
• Kavalieros Jack T
• Dewey Gilbert
• Chu-Kung Benjamin
• Sung Seung Hoon
• Le Van H
• Shivaraman Shriram
• Sharma Abhishek

Classifications

• H01L29/517

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L29/42384

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic