Stacked silicon package assembly having thermal management

Patent metadata

Field	Value
Publication number	US-2020105642-A1
Application number	US-201816147286-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

First claim

What is claimed is:

1 . A chip package assembly comprising:
a substrate; a first integrated circuit (IC) die mounted to the substrate; a cover disposed over the first IC die; and a plurality of extra-die conductive posts disposed between the cover and substrate, the plurality of extra-die conductive posts providing a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

2 . The chip package assembly of claim 1 further comprising:
a dielectric filler disposed between the substrate and the cover disposed over the die, the dielectric filler having a plurality of holes in which the plurality of extra-die conductive posts are disposed.

3 . The chip package assembly of claim 2 , wherein a first conductive post of the plurality of extra-die conductive posts further comprises:
a heat pipe having a first end exposed through a first hole of the plurality of holes and in conductive thermal contact with the cover, the heat pipe having a second end exposed through the first hole and in conductive thermal contact with the substrate.

4 . The chip package assembly of claim 1 , wherein the plurality of extra-die conductive posts each further comprises:
a seed layer disposed on the substrate; and a bulk thermally conductive layer disposed on the seed layer.

5 . The chip package assembly of claim 1 further comprising:
a second IC die mounted to the substrate, the second IC die configured as a memory die and the first IC die configured as a logic die.

6 . The chip package assembly of claim 5 further comprising:
a stiffener bonded to the substrate and circumscribing the first and second IC dies.

7 . The chip package assembly of claim 6 , wherein at least a first conductive post of the plurality of extra-die conductive posts is disposed between one of the first and second IC dies and the stiffener.

8 . The chip package assembly of claim 7 , wherein at least a second conductive post of the plurality of extra-die conductive posts is disposed between the first and second IC dies.

9 . The chip package assembly of claim 1 , wherein a first conductive post of the plurality of extra-die conductive posts is comprises of a thermally conductive material selected from the group consisting powder, metal wool, discrete shapes, solder paste, metal fibers, metal powder, metal particles, metal balls, and thermally conductive adhesive.

10 . A high bandwidth memory chip package assembly comprising:
a substrate; at least a first memory die mounted to the substrate; at least a first logic die mounted to and communicatively coupled to the substrate; a cover disposed over the first memory die and the first logic die; a dielectric filler disposed around the first memory die and the first logic die, the dielectric filler disposed between the substrate and the cover, the dielectric filler having at least one hole; and a first conductive post disposed in the hole in the dielectric filler and providing a heat transfer path between the cover and substrate.

11 . The chip package assembly of claim 10 , wherein the conductive post further comprises:
a seed layer disposed on the substrate; and a bulk thermally conductive layer disposed on the seed layer.

12 . The chip package assembly of claim 10 further comprising:
a stiffener bonded to the substrate and circumscribing the first memory die and the first logic die.

13 . A method for fabricating a chip package assembly, the method comprising:
mounting a first integrated circuit (IC) die to a substrate; forming extra-die thermally conductive posts outward of the first IC die on the substrate; and; mounting a cover over the first IC die and the extra-die conductive posts.

14 . The method of claim 13 , wherein forming the extra-die thermally conductive posts further comprises:
forming a hole in a dielectric filler disposed around the first IC die; and filling the hole with a bulk thermally conductive layer.

15 . The method of claim 14 , wherein filling the hole with a bulk thermally conductive layer further comprises:
forming the bulk thermally conductive layer on a seed layer.

16 . The method of claim 13 , wherein forming the extra-die thermally conductive posts further comprises:
depositing the extra-die conductive posts on the substrate; and depositing a bulk thermally conductive layer around the extra-die conductive posts and the first IC die.

17 . The method of claim 16 , wherein depositing the extra-die conductive posts on the substrate further comprises:
depositing a seed layer on the substrate; opening holes in a sacrificial layer disposed on the seed layer; forming the extra-die conductive posts on a first portion the seed layer exposed through the holes; removing the sacrificial layer and a second portion of the seed layer not covered by the extra-die conductive posts; and depositing the bulk thermally conductive layer around the extra-die conductive posts and the first IC die.

18 . The method of claim 13 further comprising:
mounting a second IC die to the substrate, the second IC die configured as a memory die and the first IC die configured as a logic die.

19 . The method of claim 18 further comprising:
mounting stiffener to the substrate and around the first and second IC dies.

20 . The method of claim 13 , wherein forming the extra-die thermally conductive posts further comprises:
plating copper on the substrate or conductively coupling a heat pipe in disposed in a hole formed in a dielectric filler surrounding the IC dies to the substrate.

Assignees

• Xilinx Inc

Inventors

• Gandhi Jaspreet Singh
• Refai-Ahmed Gamal
• Liu Henley
• Kim Myongseob
• Lee Tien-Yu
• Ramalingam Suresh
• Chang Cheang-Whang

Classifications

• H01L21/481

  Electricity · mapped topic

• H01L25/18

  Electricity · mapped topic

• H01L23/427 Primary

  Electricity · mapped topic

• H01L25/50

  Electricity · mapped topic

• H01L21/4871

  Electricity · mapped topic