Systems and methods for improving within die co-planarity uniformity

Patent metadata

Field	Value
Publication number	US-2020098628-A1
Application number	US-201916572920-A
Country	US
Kind code	A1
Filing date	Sep 17, 2019
Priority date	Sep 20, 2018
Publication date	Mar 26, 2020
Grant date	—

Abstract

Exemplary methods of producing a semiconductor substrate may include characterizing a substrate pattern to identify a zonal distribution of a plurality of vias and a height and a radius of each via of the plurality of vias. The methods may include determining a fill rate for each via within the zonal distribution of the plurality of vias. The methods may include modifying a die pattern to adjust via fill rates between two zones of vias. The methods may also include producing a substrate according to the die pattern.

First claim

What is claimed is:

1 . A method of producing a semiconductor substrate, the method comprising:
characterizing a substrate pattern to identify a zonal distribution of a plurality of vias and a height and a radius of each via of the plurality of vias; determining a fill rate for each via within the zonal distribution of the plurality of vias; modifying a die pattern to adjust via fill rates between two zones of vias; and producing a substrate according to the die pattern.

2 . The method of producing a semiconductor substrate of claim 1 , wherein the modifying comprises increasing or decreasing via radius on one zone of the two zones of vias on the die pattern.

3 . The method of producing a semiconductor substrate of claim 1 , wherein the modifying comprises increasing or decreasing a percentage open area in one zone of the two zones of vias on the die pattern.

4 . The method of producing a semiconductor substrate of claim 1 , further comprising filling vias on the substrate with a first metal followed by a second metal, wherein the second metal is characterized by a melting temperature below a melting temperature of the first metal.

5 . The method of producing a semiconductor substrate of claim 4 , further comprising performing a reflow operation of the second metal to produce an arcuate shape for the second metal within each via.

6 . The method of producing a semiconductor substrate of claim 5 , wherein the vias are filled to a height where an average fill height of the second metal is less than or about twice an average via radius of the plurality of vias.

7 . The method of producing a semiconductor substrate of claim 6 , wherein, subsequent the reflow operation, at least one via characterized by a pre-flow fill height of the second metal greater than the average fill height of the second metal is characterized by a post-reflow fill height less than the pre-flow fill height of the second metal.

8 . The method of producing a semiconductor substrate of claim 6 , wherein, subsequent the reflow operation, at least one via characterized by a pre-flow fill height of the second metal less than the average fill height of the second metal is characterized by a post-reflow fill height greater than the pre-flow fill height of the second metal.

9 . A method of filling vias in a semiconductor substrate, the method comprising:
plating a metal within a plurality of vias on the semiconductor substrate, wherein a target average fill thickness of the metal within the plurality of vias is between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias, and wherein at least one via of the plurality of vias is filled to a height below the target average fill thickness of the metal; and heating the metal to cause reflow of the metal within each via of the plurality of vias, wherein the reflow adjusts the metal within the at least one via to increase in height towards the target average fill thickness.

10 . The method of filling vias in a semiconductor substrate of claim 9 , wherein the target average fill thickness of the metal within the plurality of vias is about equal to the average via radius of the plurality of vias times about 1.5 to about 2.

11 . The method of filling vias in a semiconductor substrate of claim 9 , wherein the metal is a first metal and wherein the first metal is formed overlying a second metal within each via of the plurality of vias.

12 . The method of filling vias in a semiconductor substrate of claim 11 , wherein the first metal is characterized by a melting point below or about 200° C.

13 . The method of filling vias in a semiconductor substrate of claim 11 , wherein the first metal comprises tin silver, and wherein the second metal comprises one or more metals selected from the group consisting of copper, cobalt, nickel, and tungsten.

14 . The method of filling vias in a semiconductor substrate of claim 13 , further comprising a third metal formed within each via of the plurality of vias, wherein the second metal comprises copper, and wherein the third metal comprises nickel.

15 . The method of filling vias in a semiconductor substrate of claim 9 , wherein adjusting the metal within the at least one via of the plurality of vias comprises modifying a geometry of the metal within the at least one via of the plurality of vias.

16 . The method of filling vias in a semiconductor substrate of claim 15 , wherein the metal is characterized by a pre-reflow cylindrical geometry and wherein the metal is characterized by a post-reflow hemispherical geometry.

17 . The method of filling vias in a semiconductor substrate of claim 9 , further comprising a second via of the plurality of vias separate from the at least one via and having the metal within the via filled to a height above the target average fill thickness of the metal, wherein the reflow adjusts the metal within the second via to decrease in height towards the target average fill thickness of the metal.

18 . A method of producing a semiconductor substrate, the method comprising:
characterizing a substrate pattern to identify a zonal distribution of a plurality of vias and a height and a radius of each via of the plurality of vias; determining a fill rate for each via within the zonal distribution of the plurality of vias; modifying a die pattern to adjust via fill rates between two zones of vias; producing a semiconductor substrate according to the die pattern; plating a metal within the plurality of vias on the semiconductor substrate produced, wherein a target average fill thickness of the metal within the plurality of vias is between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias, and wherein at least one via of the plurality of vias is filled to a height below the target average fill thickness of the metal; and heating the metal to cause reflow of the metal within each via of the plurality of vias, wherein the reflow adjusts the metal within the at least one via to increase in height towards the target average fill thickness.

19 . The method of producing a semiconductor substrate of claim 18 , wherein, subsequent the reflow, a total fill height of metal within each via of the plurality of vias is within 5% of an average total fill height of metal within each via of the plurality of vias.

20 . The method of producing a semiconductor substrate of claim 18 , further comprising a second via of the plurality of vias separate from the at least one via and having the metal within the via filled to a height above the target average fill thickness of the metal, wherein the reflow adjusts the metal within the second via to decrease in height towards the target average fill thickness of the metal.

Assignees

• Applied Materials Inc

Inventors

• Mchugh Paul
• Roh Kwan Wook
• Wilson Gregory J

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title