Void-free high aspect ratio metal alloy interconnects and method of manufacture using a solvent-based etchant

Patent metadata

Field	Value
Publication number	US-2020098626-A1
Application number	US-201816139241-A
Country	US
Kind code	A1
Filing date	Sep 24, 2018
Priority date	Sep 24, 2018
Publication date	Mar 26, 2020
Grant date	—

Abstract

An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a dielectric layer on a substrate; an open structure in the dielectric layer; a void-free metal-alloy interconnect formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

2 . The integrated circuit structure of claim 1 , wherein the metal-alloy comprises 50-90% of a base metal and 10-50% of a second metal element.

3 . The integrated circuit structure of claim 1 , wherein the metal-alloy is selected from a group comprising nickel-cobalt, nickel-tungsten, cobalt-tungsten, and nickel-cobalt-tungsten.

4 . The integrated circuit structure of claim 1 , wherein the metal-alloy is selected from a group comprising nickel, cobalt, tungsten, ruthenium, molybdenum, vanadium, chromium.

5 . The integrated circuit structure of claim 1 , wherein the open structure has an aspect ratio of at least 5-1.

6 . The integrated circuit structure of claim 1 , wherein the open structure comprises one of a trench and a via.

7 . The integrated circuit structure of claim 6 , wherein the trench and has an aspect ratio of 5-1 to 7-1.

8 . The integrated circuit structure of claim 6 , wherein the via and has an aspect ratio of 12-1 to 20-1 and an opening having a critical dimension less than 50 nm.

9 . A method of fabricating an integrated circuit, the method comprising:
a) forming a first dielectric layer above a substrate; b) patterning the first dielectric layer to form a first series of high aspect ratio open structures; c) depositing a metal-alloy in the first series of high aspect ratio open structures, where in due to the high aspect ratio of the first series of high aspect ratio open structures, voids are formed in the metal-alloy; d) planarizing the metal-alloy to a top surface of the first dielectric layer; e) recessing the metal-alloy to a portion of a height of the first series of high aspect ratio open structures using a solvent-based etchant to remove the voids; and f) refilling the first series of high aspect ratio open structures with the metal-alloy to form a first series of void free metal-alloy interconnects.

10 . The method of claim 9 , further comprising forming a second dielectric layer over the first series of void free metal-alloy interconnects and repeating steps b) through f) to create a second series of second void free metal-alloy interconnects over the first series of void free metal-alloy interconnects.

11 . The method of claim 9 , further comprising selecting the metal-alloy from a group comprising nickel, cobalt, tungsten, ruthenium, molybdenum, vanadium, chromium.

12 . The method of claim 9 , further comprising forming the solvent-based etchant to comprise approximately 1.0%-2% citric acid, 0.1%-0.5% peroxide, 80%-90% 1,2 propanediol or 1,3 propanediol, and 7.5%-18.9% deionized water.

13 . The method of claim 9 , further comprising patterning the first series of high aspect ratio open structures to have an aspect ratio of at least 5-1.

14 . The method of claim 9 , further comprising patterning the first series of high aspect ratio open structures to include trenches and vias.

15 . The method of claim 14 , further comprising patterning the trenches to have an aspect ratio of 5-1 to 7-1.

16 . The method of claim 14 , further comprising patterning the vias to have an aspect ratio of 12-1 to 20-1.

17 . The method of claim 16 , further comprising patterning the vias to have a critical dimension less than 50 nm.

18 . The method of claim 9 , further comprising etching the recessed metal-alloy to a roughness of less than 1.25 RMS per nm.

19 . The method of claim 9 , further comprising processing the solvent-based etchant from 90 seconds to 150 seconds.

20 . The method of claim 9 , wherein the refilling the first series of high aspect ratio open structures with the metal-alloy further comprises planarizing the refilled first series of high aspect ratio open structures.

21 . The method of claim 9 , further comprising substituting a metal for the metal-alloy.

22 . The method of claim 10 , wherein forming the second dielectric layer over the first series of void free metal-alloy interconnects further comprises: selecting a material for the second dielectric layer from the group of TiO, TiO2, ZrO, ZrO2, TaO2.

23 . An etchant comprising: approximately 1.0%-2% citric acid, 0.1%-0.5% peroxide, 80%-90% 1,2 propanediol or 1,3 propanediol, and 7.5%-18.9% deionized water.

24 . The etchant of claim 23 , wherein the etchant is used to etch a metal-alloy used as an interconnect in an integrated circuit.

25 . The etchant of claim 24 , wherein the interconnect has an aspect ratio of at least 5-1.

Assignees

• Intel Corp

Inventors

• Chowdhury Shaestagir
• Surawanvijit Sirikarn
• Saha Biswadeep
• Thompson Erica J

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• C09K13/00

  Etching, surface-brightening or pickling compositions (for glass C03C15/00, {C03C25/66; for mortars, concrete, artificial or natural stone or ceramics C04B41/5338}; for metallic material C23F, C23G1/00, C25F1/00; {for semi-conductors H10P52/40}) · CPC title

• C22C19/07

  based on cobalt · CPC title

• C22C19/03 Primary

  based on nickel · CPC title

• H01L23/5226

  Electricity · mapped topic