Method of fabricating semiconductor strucutre

Patent metadata

Field	Value
Publication number	US-2020098583-A1
Application number	US-201916693389-A
Country	US
Kind code	A1
Filing date	Nov 25, 2019
Priority date	Nov 12, 2017
Publication date	Mar 26, 2020
Grant date	—

Abstract

A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.

First claim

What is claimed is:

1 . A method, comprising:
anisotropically etching a semiconductor substrate comprising:
performing first cycles followed by second cycles, each cycle among the first and second cycles respectively comprising a passivating step followed by an etching step,
during the first cycles, a first duration ratio of the etching step to the passivating step ramps up step by step,
during the second cycles, a second duration ratio of the etching step to the passivating step is constant.

2 . The method according to claim 1 , wherein the first duration ratio non-linearly ramps up step by step, and the second duration ratio is greater than the first duration ratio.

3 . The method according to claim 1 , wherein the first duration ratio ramps up step by step from X 1 to Y 1 , X 1 is less than 1, and Y 1 is greater than 1 and less than the second duration ratio.

4 . The method according to claim 1 , wherein anisotropically etching the semiconductor substrate further comprises performing third cycles after performing the second cycles, each cycle among the third cycles respectively comprises a passivating step followed by an etching step,
during the third cycles, a third duration ratio of the etching step to the passivating step ramps up step by step.

5 . The method according to claim 4 , wherein the third duration ratio linearly ramps up step by step.

6 . The method according to claim 4 , wherein the third duration ratio ramps up step by step from X 2 to Y 2 , and X 2 and Y 2 are greater than 1 and less than the second duration ratio.

7 . The method according to claim 4 , wherein the first cycles and the second cycles are performed when a platen operates at a first frequency, and the third cycles are performed when a platen operates at a second frequency lower than the first frequency.

8 . A method, comprising:
forming a mask layer on a semiconductor substrate; anisotropically etching the semiconductor substrate revealed by the mask layer to form a first cavity and a first bump in the first cavity; removing portions of the mask layer, the portions of the mask layer covering the first bump; and after removing the portions of the mask layer, anisotropically etching the semiconductor substrate until the first cavity is deepened to form a second cavity and a second bump is formed in the second cavity, wherein the first cavity is deepened by performing cycles each comprising a passivating step followed by an etching step, during a first number of the cycles, a first duration ratio of the etching step to the passivating step ramps up step by step, during a second number of the cycles, a second duration ratio of the etching step to the passivating step is constant.

9 . The method according to claim 8 , wherein forming the mask layer on the semiconductor substrate comprises:
forming a patterned hard mask layer on the semiconductor substrate; and forming a patterned photoresist layer on the semiconductor substrate revealed by the patterned hard mask layer.

10 . The method according to claim 8 , wherein the first duration ratio non-linearly ramps up step by step, and the second duration ratio is greater than the first duration ratio.

11 . The method according to claim 8 , wherein the first duration ratio ramps up step by step from X 1 to Y 1 , X 1 is less than 1, and Y 1 is greater than 1 and less than the second duration ratio.

12 . The method according to claim 8 , wherein the first cavity is deepened by a third number of the cycles performed after performing the second number of the cycles, during the third number of the cycles, a third duration ratio of the etching step to the passivating step ramps up step by step.

13 . The method according to claim 12 , wherein the third duration ratio linearly ramps up step by step.

14 . The method according to claim 12 , wherein the third duration ratio ramps up step by step from X 2 to Y 2 , and X 2 and Y 2 are greater than 1 and less than the second duration ratio.

15 . The method according to claim 12 , wherein the first number of the cycles and the second number of the cycles are performed when a platen operates at a first frequency, and the third number of the cycles are performed when a platen operates at a second frequency lower than the first frequency.

16 . A method, comprising:
forming a mask layer on a semiconductor substrate; anisotropically etching the semiconductor substrate revealed by the mask layer to form a first cavity and a first bump in the first cavity; removing portions of the mask layer, the portions of the mask layer covering the first bump; and after removing the portions of the mask layer, anisotropically etching the semiconductor substrate until the first cavity is deepened to form a second cavity and a second bump is formed in the second cavity, wherein the first cavity is deepened by performing pre-coating cycles, first etching cycles performed after the pre-coating cycles, and second etching cycles performed after the first etching cycles, each cycle among the pre-coating cycles, the first etching cycles and the second etching cycles respectively comprises a passivating step followed by an etching step, during the pre-coating cycles, duration of the etching step ramps up step by step, and duration of the passivating step ramps down step by step, passivating step are constant, during the second etching cycles, duration of the etching step ramps up step by step and duration of the passivating step is constant.

17 . The method according to claim 16 , wherein during the pre-coating cycles, duration of the etching step linearly ramps up step by step, duration of the passivating step linearly ramps down step by step, and a first duration ratio ramps up step by step, during the first etching cycles, a second duration ratio is constant, during the second etching cycles, duration of the etching step linearly ramps up step by step, duration of the passivating step is constant, and a third duration ratio ramps up step by step, and wherein the second duration ratio is greater than the first duration ratio and the third duration ratio.

18 . The method according to claim 17 , wherein the first duration ratio ramps up step by step from X 1 to Y 1 , X 1 is less than 1, and Y 1 is greater than 1 and less than the second duration ratio.

19 . The method according to claim 17 , wherein the third duration ratio ramps up step by step from X 2 to Y 2 , and X 2 and Y 2 are greater than 1 and less than the second duration ratio.

20 . The method according to claim 16 , wherein the pre-coating cycles and the first etching cycles are performed when a platen operates at a first frequency, and the second etching cycles are performed when a platen operates at a second frequency lower than the first frequency.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Meng Chin-Han
• Hsu Chih-Hsien
• Chen Jr-Sheng
• Li An-Chi
• Huang Lin-Ching
• Chiang Yu-Pei

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title