Dual single-crystal backplate microphone system and method of fabricating same
US-9219963-B2 · Dec 22, 2015 · US
US2020079645A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020079645-A1 |
| Application number | US-201916565803-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 10, 2019 |
| Priority date | Sep 12, 2018 |
| Publication date | Mar 12, 2020 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A bottom semiconductor region is formed to include a main sub-region, extending through a bottom dielectric region that coats a semiconductor wafer, and a secondary sub-region which coats the bottom dielectric region and surrounds the main sub-region. First and second top cavities are formed through the wafer, delimiting a fixed body and a patterned structure that includes a central portion which contacts the main sub-region, and deformable portions in contact with the bottom dielectric region. A bottom cavity is formed through the bottom semiconductor region, as far as the bottom dielectric region, the bottom cavity laterally delimiting a stiffening region including the main sub-region and leaving exposed parts of the bottom dielectric region that contact the deformable portions and parts of the bottom dielectric region that delimit the first and second top cavities. The parts left exposed by the bottom cavity are selectively removed.
Opening claim text (preview).
1 . A method for manufacturing a microelectromechanical device, comprising: delimiting a first semiconductor wafer by a front surface and a rear surface; coating the rear surface with a bottom dielectric region; forming at least one first bottom window through the bottom dielectric region; forming a bottom semiconductor region that includes at least one first main sub-region which extends through the first bottom window and contacts the first semiconductor wafer, and a secondary sub-region which coats the bottom dielectric region and laterally surrounds the first main sub-region; selectively removing portions of the first semiconductor wafer, starting from the front surface so as to form a first top cavity and a second top cavity that extend as far as the bottom dielectric region and laterally delimit a fixed supporting body and a patterned structure, the patterned structure including a central portion which contacts the first main sub-region of the bottom semiconductor region and a number of deformable portions, interposed between the central portion and the fixed supporting body, in contact with the bottom dielectric region; selectively removing portions of the bottom semiconductor region so as to form a bottom cavity that extends through the bottom semiconductor region as far as the bottom dielectric region, and laterally delimits a stiffening region including the first main sub-region of the bottom semiconductor region, the bottom cavity also extending laterally so as to expose parts of the bottom dielectric region that contact the deformable portions and parts of the bottom dielectric region that delimit the first and second top cavities; and selectively removing the parts of the bottom dielectric region left exposed by the bottom cavity, in such a way that the first and second top cavities and the bottom cavity form an overall cavity, suspended inside which is the patterned structure. 2 . The method according to claim 1 , wherein the first semiconductor wafer is comprised of monocrystalline semiconductor material; wherein the step of forming the bottom semiconductor region comprises performing an epitaxial growth such that the first main sub-region of the bottom semiconductor region forms a monolithic monocrystalline region with the first semiconductor wafer; and wherein the secondary sub-region of the bottom semiconductor region is comprised of polycrystalline semiconductor material. 3 . The method according to claim 2 , wherein the stiffening region includes a portion of the secondary sub-region of the bottom semiconductor region that laterally surrounds the first main sub-region, the portion of the secondary sub-region coating a corresponding portion of the bottom dielectric region which is laterally staggered with respect to the parts of the bottom dielectric region that delimit the first and second top cavities; and further comprising the step of selectively removing sub-portions of the portion of the secondary sub-region, so as to expose the corresponding portion of the bottom dielectric region, and subsequently carrying out the step of selectively removing the parts of the bottom dielectric region left exposed by the bottom cavity. 4 . The method according to claim 1 , further comprising coating the front surface of the first semiconductor wafer with a top dielectric region, and forming at least one top window through the top dielectric region; and wherein the step of selectively removing portions of the first semiconductor wafer starting from the front surface comprises removing portions of the first semiconductor wafer that give out onto the top window. 5 . The method according to claim 4 , further comprising: subsequent to formation of the first and second top cavities and prior to the step of selectively removing portions of the bottom semiconductor region, fixing the first semiconductor wafer to a second semiconductor wafer via interposition of a bonding region that extends on the top dielectric region and within the first and second top cavities; and subsequent to the step of selectively removing the parts of the bottom dielectric region left exposed by the bottom cavity, separating the first semiconductor wafer from the second semiconductor wafer. 6 . The method according to claim 1 , further comprising forming a metal region on the central portion of the patterned structure. 7 . The method according to claim 1 , wherein the central portion of the patterned structure is mobile with respect to the fixed supporting body, following deformation of the number of deformable portions. 8 . The method according to claim 1 , wherein the first and second top cavities laterally delimit a number of peripheral portions, fixed with respect to the bottom dielectric region; wherein each deformable portion of the patterned structure is interposed between the central portion of the patterned structure and a corresponding peripheral portion; and further comprising manufacturing process further comprising forming a number of additional bottom windows through the bottom dielectric region, the step of forming a bottom semiconductor region further comprising forming a number of additional main sub-regions, each of which extends through a corresponding additional bottom window, is laterally staggered with respect to the first main sub-region, and contacts a corresponding peripheral portion. 9 . A microelectromechanical (MEMS) device, comprising: a fixed supporting body of semiconductor material, delimited by a rear surface; a bottom dielectric region fixed with respect to the fixed supporting body and extending underneath the rear surface; a patterned region of semiconductor material and suspended in a cavity laterally delimited by the fixed supporting body, the patterned region comprising: a central portion, which in resting conditions extends above the rear surface; and a number of deformable portions, each of which is interposed between the central portion and the fixed supporting body; and an additional semiconductor region forming, together with the central portion of the patterned region, a mobile structure, the additional semiconductor region contacting the central portion of the patterned region and extending, in resting conditions, underneath the rear surface, the mobile structure being mobile with respect to the fixed supporting body, following upon deformation of the number of deformable portions. 10 . The MEMS device according to claim 9 , wherein the central portion of the patterned region and the additional semiconductor region form a monolithic monocrystalline region. 11 . The MEMS device according to claim 9 , further comprising a metal region extending on the central portion of the patterned region. 12 . A MEMS projector system comprising a MEMS device according to claim 11 and an optical source configured to generate an optical beam that impinges upon the metal region. 13 . A portable electronic apparatus comprising a MEMS projector system according to claim 12 . 14 . The portable electronic apparatus according to claim 13 , wherein the MEMS projector system is a stand-alone accessory having a casing coupled in a releasable way to a respective casing of the portable electronic apparatus. 15 . The portable electronic apparatus according to claim 13 , wherein the MEMS projector system is formed in an integrated way, within a casing of the portable electronic apparatus. 16 . A device, comprising: a microelectromechanical (MEMS) device, comprising: a fixed supporting body of semiconductor material; a bottom dielectric region extending underneath a rear surface of t
containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) · CPC title
Micromirrors, not used as optical switches · CPC title
Cavities · CPC title
using two-dimensional electronic spatial light modulators (micromechanical modulators as such G02B26/0833; liquid crystal modulators as such G02F1/13) · CPC title
MEMS characterised by an electronic circuit specially adapted for controlling or driving the same (B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.