Power source multiplexer with adaptive switch control

Patent metadata

Field	Value
Publication number	US-2020076430-A1
Application number	US-201916279422-A
Country	US
Kind code	A1
Filing date	Feb 19, 2019
Priority date	Aug 28, 2018
Publication date	Mar 5, 2020
Grant date	—

Abstract

A power source multiplexer includes a first switch circuit connected between a first input voltage source node and an output voltage node. A second switch circuit is connected between a second input voltage source node and the output voltage node. A driver circuit is configured to provide a steady-state current to drive one of the first or second switch circuits to electrically connect the respective input voltage source node to the output voltage node. A boost circuit is configured to boost the steady-state current for a switching time interval when switching from one of the input voltage source nodes being connected to the output node to the other of the input voltage source nodes being connected to the output voltage node.

First claim

1 . A power source multiplexer, comprising:
a first switch circuit connected between a first input voltage source node and an output voltage node; a second switch circuit connected between a second input voltage source node and the output voltage node; a driver circuit configured to provide a steady-state current to drive one of the first or second switch circuits to electrically connect the respective input voltage source node to the output voltage node; and a boost circuit configured to boost the steady-state current for a switching time interval when switching from one of the input voltage source nodes being connected to the output voltage node to another of the input voltage source nodes being connected to the output voltage node.

2 . The power source multiplexer of claim 1 , wherein the driver circuit includes a first driver circuit and a second driver circuit, the first driver circuit includes:
a first steady-state circuit configured to provide a first steady-state current to drive the first switch circuit to electrically connect the first input voltage source node to the output voltage node; and a first boost circuit configured to boost the first steady-state current for the switching time interval; the second driver circuit includes: a second steady-state circuit configured to provide a second steady-state current to drive the second switch circuit to electrically connect the second input voltage source node to the output voltage node; and a second boost circuit configured to boost the second steady-state current for the switching time interval.

3 . The power source multiplexer of claim 2 , further comprising a control logic circuit configured to generate control signals to control each of the first driver circuit and the second driver circuit.

4 . The power source multiplexer of claim 3 , wherein the first switch circuit comprises transistor switch devices connected in series and configured to switch the first input voltage source node to the output voltage node in response to respective control signals, and
wherein the second switch circuit includes transistor switch devices connected in series and configured to switch the second input voltage source node to the output voltage node in response to respective control signals.

5 . The power source multiplexer of claim 4 , wherein the transistor switch devices connected in series is a drain-to-drain connection or a source-to-source connection between the switch devices.

6 . The power source multiplexer of claim 4 ,
wherein the first steady-state circuit further comprises steady-state switch devices that are configured to connect first steady-state current sources to apply steady-state current to the respective series-connected transistor switch devices of the first switch circuit in response to the respective control signals when the first input voltage source node is connected to the output voltage node; wherein the first boost circuit further comprises first boost switch devices that are configured to connect respective boost current sources to apply boost current to the series-connected transistor switch devices of the first switch circuit in response to the control signals during a switching time interval for a transition from the from the second input voltage source node being connected to the output voltage node to the first input voltage source node being connected to the output voltage node, wherein the second steady-state circuit further comprises steady-state switch devices that are configured to connect second steady-state current sources to apply steady-state current to the series-connected transistor switch devices of the second switch circuit in response to the respective control signals when the second input voltage source node is connected to the output voltage node, wherein the second boost circuit further comprises second boost switch devices that are configured to connect respective boost current sources to apply boost current to the series-connected transistor switch devices of the second switch circuit in response to the control signals during a switching time interval for a transition from the first input voltage source node being connected to the output voltage node to the second input voltage source node being connected to the output voltage node.

7 . The power source multiplexer of claim 6 , wherein the control logic circuit is configured to control on-time of the respective boost switches based on comparing current in one of the transistor switch devices with respect to a reference current.

8 . The power source multiplexer of claim 3 , wherein the first input voltage source node is configured at a higher voltage potential than the second input voltage source node, and
wherein the control logic circuit further comprises a reverse current blocking circuit configured to delay connecting the second input voltage source node to the output voltage node based on comparing the output voltage node to a blocking threshold voltage that is based on the second input voltage source node and an offset voltage.

9 . The power source multiplexer of claim 3 wherein the control logic circuit further comprises a priority circuit configured to trigger a switchover from one input source node to a priority source in response detecting a voltage of the priority source crossing a priority threshold.

10 . The power source multiplexer of claim 3 , wherein the control logic circuit further comprises a programming circuit configured to enable setting of at least one of a reference current threshold, a reverse current blocking threshold, a priority threshold, and to select one of the input voltage source nodes as a priority node.

11 . The power source multiplexer of claim 1 , wherein the first switch circuit, the second switch circuit, the driver circuit, and the boost circuit are implemented as an integrated circuit (IC) chip.

12 . A device, comprising:
a first switch circuit having a first control input, a first source input, and a first output coupled to an output node; a first boost circuit having a first boost input and a first boost output, the first boost output coupled to the first control input of the first switch circuit; a first steady-state circuit having a first steady-state input and a first steady-state output, the first steady-state output coupled to the first control input of the first switch circuit; a second switch circuit having a second control input, a second source input and a second output coupled to the output node; a second boost circuit having a second boost input and a second boost output, the second boost output coupled to the second control input of the second switch circuit; a second steady-state circuit having a second steady-state input and a second steady-state output, the second steady-state output coupled to the second control input of the second switch circuit; and a control logic circuit having respective outputs coupled to each of the first boost input, the first steady-state input, the second boost input, and the second steady-state input.

13 . The device of claim 12 , wherein the first boost circuit and the second boost circuit are configured to boost a steady-state current of the first steady-state circuit or the second steady-state circuit for a switching time interval when switching from one of the first source input to the output node or the second source input to the output node.

14 . The device of claim 12 , wherein each of the first switch circuit and the second switch circuit includes transistor switch devices connected in series and configured to switch the respective input voltage source node to the outpu

Assignees

• Texas Instruments Inc

Inventors

• Turkson Richard
• Beck Sungho
• Choi Jae Won
• Klarenbeek Johnny

Classifications

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title