Adjustable power rail multiplexing

Patent metadata

Field	Value
Publication number	US-9852859-B2
Application number	US-201514981183-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first power rail;
a second power rail;
a load power rail;
multiple power-multiplexer tiles coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation, each power-multiplexer tile configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail; and
adjustment circuitry configured to adjust at least one order in which the multiple power-multiplexer tiles perform at least a portion of the power-multiplexing operation.

2. The integrated circuit of claim 1 , wherein:
the power-multiplexing operation is effectuated across the chained arrangement of the multiple power-multiplexer tiles;
the power-multiplexing operation includes a disconnection portion and a connection portion;
the multiple power-multiplexer tiles are configured to perform the disconnection portion of the power-multiplexing operation in a sequential order; and
the adjustment circuitry is further configured to cause the multiple power-multiplexer tiles to perform the connection portion of the power-multiplexing operation in a non-sequential order.

3. The integrated circuit of claim 2 , wherein the adjustment circuitry is further configured to enable at least one power-multiplexer tile of the multiple power-multiplexer tiles to perform the connection portion of the power-multiplexing operation out of an order that is determined by a series coupling of the chained arrangement of the multiple power-multiplexer tiles.

4. The integrated circuit of claim 3 , wherein the adjustment circuitry is further configured to provide to the at least one power-multiplexer tile an input feedback control signal selected from a preset signal set to a logical high value or an output feedback control signal produced by a preceding power-multiplexer tile.

5. The integrated circuit of claim 4 , wherein:
the at least one power-multiplexer tile is configured to connect the load power rail to the second power rail responsive to the input feedback control signal having the logical high value; and
the adjustment circuitry is further configured to select the preset signal as the input feedback control signal for the at least one power-multiplexer tile to enable the at least one power-multiplexer tile to couple the load power rail to the second power rail out of the order that is determined by the series coupling of the chained arrangement of the multiple power-multiplexer tiles.

6. The integrated circuit of claim 3 , wherein the adjustment circuitry is further configured to provide to the at least one power-multiplexer tile an input feedback control signal that is set to a logical high value to enable the at least one power-multiplexer tile to couple the load power rail to the second power rail out of the order that is determined by the series coupling of the chained arrangement of the multiple power-multiplexer tiles.

7. The integrated circuit of claim 6 , wherein the adjustment circuitry is further configured to provide a feedback adjustment signal that is tied to a preset value to cause the input feedback control signal to be coupled to a preset signal set to a logical high value.

8. The integrated circuit of claim 1 , wherein:
the multiple power-multiplexer tiles are further configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail in at least one sequential order to avoid creation of a short-circuit current condition between the first power rail and the second power rail in one mode; and
the adjustment circuitry is further configured to enable adjustment of a duration for which the load power rail is coupled to both the first power rail and the second power rail in another mode by enabling one or more power-multiplexer tiles of the multiple power-multiplexer tiles to selectively couple the load power rail to the second power rail out of the at least one sequential order.

9. The integrated circuit of claim 8 , wherein a length of the duration is controllable based on a number of intervening power-multiplexer tiles between one power-multiplexing tile that is last in the chained arrangement of the multiple power-multiplexer tiles and another power-multiplexer tile that is first to be enabled to couple the load power rail to the second power rail out of the at least one sequential order.

10. The integrated circuit of claim 1 , wherein each power-multiplexer tile of the multiple power-multiplexer tiles includes:
a first switch configured to connect or disconnect the load power rail to or from the first power rail;
a second switch configured to connect or disconnect the load power rail to or from the second power rail; and
a delay control circuit configured to prevent the first switch and the second switch of a given power-multiplexer tile from being closed simultaneously.

11. The integrated circuit of claim 10 , wherein the delay control circuit comprises self-timed circuitry that is independent of a periodic clock signal.

12. The integrated circuit of claim 1 , wherein the adjustment circuitry is further configured to cause a temporal overlap region in which one power-multiplexer tile of the multiple power-multiplexer tiles is coupling the load power rail to the first power rail and another power-multiplexer tile of the multiple power-multiplexer tiles is coupling the load power rail to the second power rail.

13. The integrated circuit of claim 1 , wherein:
the multiple power-multiplexer tiles comprise multiple first power-multiplexer tiles that form a first chained series of power-multiplexer tiles;
the integrated circuit further comprises a second chained series of power-multiplexer tiles including multiple second power-multiplexer tiles coupled in series in a chained arrangement and configured to jointly perform the power-multiplexing operation; and
the adjustment circuitry is further configured to establish a duration of a short-circuit current condition created between the first power rail and the second power rail by coordinating operation of the first chained series of power-multiplexer tiles and the second chained series of power-multiplexer tiles.

14. An integrated circuit comprising:
a first power rail;
a second power rail;
a load power rail;
multiple power-multiplexer tiles coupled in series in a chained arrangement and configured to perform a power-multiplexing operation including switching between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail, the power-multiplexing operation having at least one order that is determined by the series in which the multiple power-multiplexer tiles are coupled for the chained arrangement; and
adjustment means for adjusting the at least one order in which the multiple power-multiplexer tiles are to perform at least a portion of the power-multiplexing operation.

15. The integrated circuit of claim 14 , wherein the adjustment means comprises means for establishing a duration that a short-circuit current condition exists between the first power rail and the second power rail across different power-multiplexer tiles during the power-multiplexing operation.

16. The integrated circuit of claim 14 , wherein the adjustment means comprises means for enabling a particular power-multiplexer tile of the multiple power-multiplexer tiles to perform at least part of the power-multiplexing operation out of the at least one order.

17. The integrated circuit of claim 14 , wh

Assignees

• Qualcomm Inc

Inventors

• Cao Lipeng
• Kumar Dorav
• Zafar Bilal
• Vilangudipitchai Ramaprasath
• Narayanan Venkatasubramanian
• Luo Xi

Classifications

• H01H47/00 Primary

  Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title