Memory circuit and method of operating a memory circuit

Patent metadata

Field	Value
Publication number	US-2020066312-A1
Application number	US-201916666425-A
Country	US
Kind code	A1
Filing date	Oct 29, 2019
Priority date	Dec 7, 2016
Publication date	Feb 27, 2020
Grant date	—

Abstract

A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

First claim

What is claimed is:

1 . A method of operating a memory circuit, the memory circuit comprising a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, and a plurality of word lines, each word line coupled with at least one memory cell of the plurality of memory cells, the method comprising:
storing a base word in a portion of a word line of the plurality of word lines, wherein the base word includes a sequence of known bits; and forming a modified data word comprising writing a data word to the portion of a word line, wherein the data word comprises a sequence of data bits and wherein writing the data word comprises combining the sequence of data bits of the data word with the sequence of known bits of the base word using a logic bitwise AND operation or a logic bitwise OR operation.

2 . The method of claim 1 , further comprising:
reading the modified data word; forming a test word comprising performing a logic bitwise AND operation or a logic bitwise OR operation on the data word and the base word; and comparing the modified data word to the test word.

3 . The method of claim 1 ,
wherein the sequence of known bits of the base word comprises n bits, wherein approximately n/2 bits are in a first bit state, and the remaining bits of the sequence of known bits are in a second bit state.

4 . The method of claim 1 ,
wherein the base word comprises a random word having a pre-defined number of zeros.

5 . The method of claim 1 , further comprising:
invalidating the modified data word by inverting at least one bit of the modified data word.

6 . The method of claim 1 , wherein the data word comprises an equal number of ones and zeros.

7 . The method of claim 1 , further comprising:
iteratively forming a subsequent modified data, which for each iteration, comprises:
forming a modified data word by combining a sequence of data bits of a subsequent data word with a sequence of bits of a modified data word formed in a previous iteration by performing a logic bitwise AND operation or a logic bitwise OR operation, wherein the subsequent data words of respective iterations include different values.

8 . A memory circuit, comprising:
a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, and a plurality of word lines, each word line coupled with at least one memory cell of the plurality of memory cells, wherein the memory circuit is configured to: store a base word in a portion of a word line of the plurality of word lines, wherein the base word includes of a sequence of known bits; and form a modified data word comprising the memory circuit to write a data word to the portion of a word line, wherein the data word includes a sequence of data bits, and wherein the memory circuit configured to write the data word comprises the memory to combine the sequence of data bits of the data word with the sequence of known bits of the base word using a logic bitwise AND operation or a logic bitwise OR operation.

9 . The memory circuit of claim 8 , wherein the memory circuit is further configured to:
read the modified data word; form a test word comprising the memory circuit to perform a logic bitwise AND operation or a logic bitwise OR operation on the data word and the base word; and compare the modified data word to the test word.

10 . The memory circuit of claim 8 ,
wherein the sequence of known bits of the base word comprises n bits, wherein approximately n/2 bits are in a first bit state, and the remaining bits of the sequence of known bits are in a second bit state.

11 . The memory circuit of claim 8 ,
wherein the base word comprises a random word having a pre-defined number of zeros.

12 . The memory circuit of claim 8 , wherein the memory circuit is further configured to:
invert at least one bit of the modified data word so as to invalidate the modified data word.

13 . The memory circuit of claim 8 , wherein the data word comprises an equal number of ones and zeros.

14 . The memory circuit of claim 8 , wherein the memory circuit is further configured to iteratively form a subsequent modified data, which for each iteration, the memory circuit is configured to:
form a modified data word comprising the memory circuit to combine a sequence of data bits of a subsequent data word with a sequence of bits of a modified data word formed in a previous iteration through a logic bitwise AND operation or a logic bitwise OR operation, wherein the subsequent data words of respective iterations include different values.

15 . A method for operating a memory circuit, the memory circuit comprising a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, and a plurality of word lines, each word line coupled with at least one memory cell of the plurality of memory cells, the method comprising:
forming a modified word comprising writing a first random value to a word line portion, wherein the word line portion includes an erased word of n number of bits and wherein the first random value including r1 number of bits, wherein r1 is less than n, wherein writing the first random value comprises combining the random value with the erased word using a logic bitwise AND operation or a logic bitwise OR operation; writing a second random value to the word line portion, wherein the second random value includes r2 number of bits, wherein r1+r2 is less than or equal to n, and wherein writing the second random value to the word line portion comprises combining the second random value with the modified word using a logic bitwise AND operation or a logic bitwise OR operation at bit positions of the modified word that were not previously modified by bits of the first random value.

Assignees

• Infineon Technologies Ag

Inventors

• Otterstedt Jan
• Boch Robin
• Dirscherl Gerd
• Meyer Bernd
• Peters Christian
• Sonnekalb Steffen

Classifications

• G11C16/105

  Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C2029/2602

  Concurrent test · CPC title

• H03M13/13

  Linear codes · CPC title