Managing capacitor voltage dependence
US-2024396537-A1 · Nov 28, 2024 · US
US2020044906A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020044906-A1 |
| Application number | US-201816054261-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 3, 2018 |
| Priority date | Aug 3, 2018 |
| Publication date | Feb 6, 2020 |
| Grant date | — |
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A digital triggering system for processing data relating to a signal received is described, with an analog-to-digital converter, an IQ data source providing IQ data, a first digital signal processor, and at least a second digital signal processor. The first digital signal processor is connected with the IQ data source via a first signal path. The second digital signal processor is connected with the IQ data source via a second signal path. The first digital signal processor has at least a first signal processing parameter. The second digital signal processor has at least a second signal processing parameter. The first signal processing parameter and the second signal processing parameter are independent from each other. The first digital signal processor generates a trigger signal based upon a characteristic of the IQ data obtained from the IQ data source. The first digital signal processor triggers the second digital signal processor via the trigger signal to acquire IQ data obtained from the IQ data source. Further, a method for processing data is described.
Opening claim text (preview).
1 . A digital triggering system for processing data relating to a signal received, comprising: an analog-to-digital converter for converting an analog input signal into a digital signal; an In-phase and Quadrature-phase (IQ) data source providing IQ data; a first digital signal processor located downstream of said IQ data source; and at least a second digital signal processor located downstream of said IQ data source, said first digital signal processor being connected with said IQ data source via a first signal path so that said first digital signal processor obtains the IQ data provided by said IQ data source; said second digital signal processor being connected with said IQ data source via a second signal path so that said second digital signal processor obtains the IQ data provided by said IQ data source; said first digital signal processor having at least a first signal processing parameter and said second digital signal processor having at least a second signal processing parameter such that both digital signal processors are enabled to use different data portions of the IQ data provided, said first signal processing parameter and said second signal processing parameter being independent from each other; said first digital signal processor generating a trigger signal based upon a characteristic of the IQ data obtained from said IQ data source; and said first digital signal processor triggering said second digital signal processor via said trigger signal to acquire IQ data obtained from said IQ data source. 2 . The digital triggering system of claim 1 , wherein said first digital signal processor and said second digital signal processor have different signal processing parameters. 3 . The digital triggering system of claim 1 , wherein said first digital signal processor and said second digital signal processor are configured to capture the signal received on different portions of the spectrum of the signal. 4 . The digital triggering system of claim 1 , wherein said first digital signal processor also acquires IQ data obtained from said IQ data source. 5 . The digital triggering system of claim 4 , wherein said IQ data acquired by said first digital signal processor and said IQ data acquired by said second digital signal processor relate to different portions of the spectrum of said signal received. 6 . The digital triggering system of claim 1 , wherein said first digital signal processor and said second digital signal processor are connected with each other via a trigger line via which said first digital signal processor forwards said trigger signal to said second digital signal processor. 7 . The digital triggering system of claim 1 , wherein said first signal path and said second signal path both branch off from a common signal path line connected to said IQ data source. 8 . The digital triggering system of claim 1 , wherein said first digital signal processor uses at least one of frequency domain triggering, time domain triggering, phase domain triggering, modulation domain triggering and demodulation domain triggering. 9 . The digital triggering system of claim 1 , wherein a temporary intermediate storage for IQ data is provided that is assigned to at least one of said first digital signal processor or said second digital signal processor. 10 . The digital triggering system of claim 1 , wherein a user interface is provided via which a user is enabled to make settings of at least one of said first digital signal processor or said second digital signal processor. 11 . The digital triggering system of claim 1 , wherein the acquisition of IQ data via said second digital signal processor can be shifted by setting an offset. 12 . The digital triggering system of claim 1 , wherein the acquisition of IQ data via said second digital signal processor is started prior to a trigger event. 13 . The digital triggering system of claim 1 , wherein said digital triggering system comprises a measurement module, said measurement module providing further analysis. 14 . The digital triggering system of claim 13 , wherein said measurement module is assigned to said second signal path for further analyzing the IQ data processed by at least one of said second signal path or said second digital signal processor. 15 . The digital triggering system of claim 1 , wherein an acquisition memory for IQ data is provided to store the IQ data acquired, said acquisition memory being connected with at least one of said first digital signal processor or said second digital signal processor. 16 . The digital triggering system of claim 1 , wherein the at least one second digital signal processor corresponds to a stage of the digital triggering system, the digital triggering system comprising several stages which receive said trigger signal from said first digital signal processor. 17 . A method for processing data, comprising: converting an analog signal into a digital signal; obtaining In-phase and Quadrature-phase (IQ) data from said digital signal; processing the IQ data obtained while a first signal processing parameter is taken into account by a first digital signal processor; generating a trigger signal via said first digital signal processor when a trigger event occurs in the IQ data processed with regard to said first signal processing parameter; and acquiring IQ data via a second digital signal processor which takes a second signal processing parameter into account that is independent from said first signal processing parameter such that both digital signal processors are enabled to use different data portions of the IQ data provided. 18 . A digital triggering system for processing data relating to a signal received, comprising: an analog-to-digital converter for converting an analog input signal into a digital signal; an In-phase and Quadrature-phase (IQ) data source providing IQ data; a first digital signal processor located downstream of said IQ data source; and at least a second digital signal processor located downstream of said IQ data source, said first digital signal processor being connected with said IQ data source via a first signal path so that said first digital signal processor obtains the IQ data provided by said IQ data source; said second digital signal processor being connected with said IQ data source via a second signal path so that said second digital signal processor obtains the IQ data provided by said IQ data source; said first digital signal processor having at least a first signal processing parameter and said second digital signal processor having at least a second signal processing parameter, said first signal processing parameter and said second signal processing parameter being independent from each other; said first digital signal processor generating a trigger signal based upon a characteristic of the IQ data obtained from said IQ data source; said first digital signal processor triggering said second digital signal processor via said trigger signal to acquire IQ data obtained from said IQ data source; and said first digital signal processor and said second digital signal processor are configured to capture the signal received on different portions of the spectrum of the signal.
Measuring or testing · CPC title
Details of sampling arrangements or methods · CPC title
Compensation for quadrature error in the received signal · CPC title
for triggering, synchronisation · CPC title
Compensation for phase rotation in the demodulated signal · CPC title
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