Method of double-side polishing semiconductor wafer

Patent metadata

Field	Value
Publication number	US-2020039021-A1
Application number	US-201716341692-A
Country	US
Kind code	A1
Filing date	Oct 3, 2017
Priority date	Nov 2, 2016
Publication date	Feb 6, 2020
Grant date	—

Abstract

Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.

First claim

1 . A method of double-side polishing of a semiconductor wafer using a double-side polishing apparatus, comprising:
a step of predetermining a criterion function for determining polishing tendencies of double-side polishing by performing multiple regression analysis based on a shape index of a plurality of semiconductor wafers having subjected to double-side polishing using the double-side polishing apparatus and on apparatus log data of the double-side polishing apparatus in a last stage of polishing corresponding to the shape index; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; subsequent to the first step, a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in the last stage of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and subsequent to the second step, a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.

2 . The method of double-side polishing a semiconductor wafer, according to claim 1 , wherein polishing time in the third step is based on the value of the criterion function.

3 . The method of double-side polishing a semiconductor wafer, according to claim 1 , wherein the adjusted polishing conditions involve adjustment of one or both of a rotation speed of plates of the double-side polishing apparatus and a load on the plates.

4 . The method of double-side polishing a semiconductor wafer, according to claim 1 , wherein the second step is started when a thickness of the semiconductor wafer reaches a predetermined thickness.

Assignees

• Sumco Corp

Inventors

• KUBOTA Mami
• Fukuhara Fumiya
• Miura Tomonori

Classifications

• H10P90/129

  by polishing · CPC title

• H10P90/124

  by processing the backside of the wafers · CPC title

• B24B37/08

  for double side lapping · CPC title

• B24B37/28 Primary

  for double side lapping of plane surfaces · CPC title

• B24B37/20 Primary

  Lapping pads for working plane surfaces · CPC title