Iii-nitride material semiconductor structures on conductive silicon substrates

Patent metadata

Field	Value
Publication number	US-2020027872-A1
Application number	US-201816039866-A
Country	US
Kind code	A1
Filing date	Jul 19, 2018
Priority date	Jul 19, 2018
Publication date	Jan 23, 2020
Grant date	—

Abstract

III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

First claim

1 . A semiconductor structure for an integrated circuit component, comprising:
a substrate, at least a portion of which is made of bulk silicon having an electronic resistivity of less than 0.10 Ω-cm when the silicon is at 25° C.; and a III-nitride material region located over the substrate.

2 . A semiconductor structure for an integrated circuit component, comprising:
a substrate, at least a portion of which comprises silicon having an electronic resistivity of less than 0.10 Ω-cm when the silicon is at 25° C.; and a III-nitride material region located over the substrate, wherein the integrated circuit component is configured to operate at a frequency greater than 50 MHz.

3 . The semiconductor structure of claim 1 , wherein the integrated circuit component is configured to operate at a frequency greater than 50 MHz.

4 . The semiconductor structure of claim 1 ,
wherein the integrated circuit component is an active device.

5 . The semiconductor structure of claim 1 ,
wherein the integrated circuit component is a discrete component.

6 . The semiconductor structure of claim 1 ,
wherein the substrate includes a silicon-on-insulator structure.

7 . The semiconductor structure of claim 2 ,
wherein the substrate comprises bulk silicon or silicon carbide.

8 . The semiconductor structure of claim 1 ,
wherein the III-nitride material region comprises gallium nitride material.

9 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises:
a nucleation layer formed over the substrate; a buffer layer formed over the nucleation layer; and a device region formed over the buffer layer.

10 . The semiconductor structure of claim 9 , further comprising a transition layer located between the nucleation layer and the buffer layer.

11 . The semiconductor structure of claim 10 , wherein the transition layer is a superlattice.

12 . The semiconductor structure of claim 10 , wherein the transition layer is compositionally graded.

13 . The semiconductor structure of claim 9 , further comprising the integrated circuit component that is formed, at least in part, in the device region.

14 . The semiconductor structure of claim 13 , wherein the integrated circuit component is a transistor or a diode.

15 . The semiconductor structure of claim 14 , wherein the transistor or diode is configured to operate at a frequency between 100 MHz and 20 GHz.

16 . The semiconductor structure of claim 14 , wherein the transistor or diode has an active-area capacitance ratio that is no larger than 0.4 pF/mm.

17 . The semiconductor structure of claim 14 , wherein an amount of power dissipated into the substrate due to capacitive coupling between components of the transistor or diode and the substrate is no larger than 0.1 Watts/mm2 when the substrate temperature is at 120° C.

18 . The semiconductor structure of claim 14 , wherein a power added efficiency of the transistor remains above 50% when the substrate temperature is increased to 125° C.

19 . A semiconductor device, comprising:
a substrate, at least a portion of which comprises silicon; a III-nitride material region having a thickness of at least 2.0 micrometers located over the substrate; a source electrode over the III-nitride material region, the source electrode defining a source electrode interfacial area with the III-nitride material region; a drain electrode over the III-nitride material region, the drain electrode defining a drain electrode interfacial area with the III-nitride material region; and a gate electrode over the III-nitride material region, the gate electrode defining a gate electrode interfacial area with the III-nitride material region; wherein:
the source electrode, and the drain electrode, and the gate electrode define an active area, and
the sum of the source electrode interfacial area, the drain electrode interfacial area, and the gate electrode interfacial area is less than 30% of the active area.

20 - 21 . (canceled)

22 . The semiconductor device of claim 19 , further comprising an integrated circuit component formed in the III-nitride material region and including the ohmic contact.

23 - 185 . (canceled)

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Boles Timothy E
• Struble Wayne Mack

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title