Self aligned buried power rail

US2020006112A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020006112-A1
Application numberUS-201916568902-A
CountryUS
Kind codeA1
Filing dateSep 12, 2019
Priority dateApr 7, 2017
Publication dateJan 2, 2020
Grant date

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

First claim

Opening claim text (preview).

What is claimed: 1 . A structure comprising: a partial fin structure of substrate material; a buried power rail comprising conductive metal fill material aligned with and over the partial fin structure; and a contact to the buried power rail. 2 . The structure of claim 1 , wherein a space between the buried power rail and neighboring fin structures is substantially equal to fin to fin spacing. 3 . The structure of claim 1 , wherein the buried power rail is a metal fill material over a liner of conductive barrier material. 4 . The structure of claim 3 , wherein the liner of conductive barrier material is a multi-layer liner. 5 . The structure of claim 4 , wherein the multi-layer liner comprises a first dielectric film to isolate electrically the substrate material and a single or bi-layer of barrier material. 6 . The structure of claim 5 , wherein the single or bi-layer of barrier material is one of TaN, TiN, Co or Ru. 7 . The structure of claim 5 , wherein the metal fill material is a high melting temperature metal. 8 . The structure of claim 1 , wherein the buried power rail is partially recessed within the partial fin structure of substrate material. 9 . The structure of claim 3 , further comprising a capping material on exposed surfaces of the metal fill material and the liner. 10 . The structure of claim 9 , further comprising a gap fill material on the capping material. 11 . The structure of claim 10 , wherein the gap fill material is recessed and the contact is within the recessed gap fill material contacting to the buried power rail.

Assignees

Inventors

Classifications

  • Power or ground buses · CPC title

  • Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

  • H10W20/021Primary

    of interconnections within wafers or substrates · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US2020006112A1 cover?
The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the seco…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/021. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 02 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).