Integrated cross-domain power transfer voltage regulators

Patent metadata

Field	Value
Publication number	US-2020004282-A1
Application number	US-201816020725-A
Country	US
Kind code	A1
Filing date	Jun 27, 2018
Priority date	Jun 27, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.

First claim

We claim:

1 . A semiconductor package comprising:
a first domain comprising first one or more circuitries; a second domain comprising second one or more circuitries; a first voltage regulator (VR) to supply power to the first domain from a power bus; a second VR to supply power to the second domain from the power bus; and a third VR coupled between the first and second domains, the third VR to at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.

2 . The semiconductor package of claim 1 , further comprising:
a substrate; and a first die and a second die stacked on the substrate, wherein the first VR comprises one or more inductors and one or more switches, wherein the first die comprises the first domain and the second domain, and wherein the second die comprises the one or more switches of the first VR.

3 . The semiconductor package of claim 2 , wherein:
the one or more inductors of the first VR are on, or embedded within, the substrate.

4 . The semiconductor package of claim 2 , wherein the one or more inductors of the first VR are first one or more inductors, wherein the one or more switches of the first VR are first one or more switches, and wherein:
the third VR comprises second one or more inductors and second one or more switches; the first die comprises the second one or more switches; and the second one or more inductors of the third VR are at least one of:
on, or embedded within, the substrate, or
on, or embedded within, the second die.

5 . The semiconductor package of claim 4 , further comprising:
a fourth VR comprising third one or more inductors and third one or more switches; and a second power bus, wherein the third VR is coupled between the first domain and the second power bus, wherein the fourth VR is coupled between the second domain and the second power bus, and wherein the first die comprises the third one or more switches of the fourth VR.

6 . The semiconductor package of claim 5 , wherein the substrate comprises the second power bus.

7 . The semiconductor package of claim 2 , wherein:
the substrate has a recess, and a non-recessed section that does not include the recess; the second die is at least in part within the recess; and the first die is stacked on the second die, such that:
a first one or more interconnect structures of the first die is coupled to the second die, and
a second one or more interconnect structures of the first die is coupled to the non-recessed section of the substrate.

8 . The semiconductor package of claim 2 , wherein:
the one or more inductors of the first VR are integrated within the first die or the second die.

9 . The semiconductor package of claim 1 , further comprising:
a fourth VR to receive input power to the apparatus, and supply power to the power bus.

10 . The semiconductor package of claim 1 , wherein the third VR is to: receive power from the first domain, and transmit power to the second domain, thereby transferring power from the first domain to the second domain.

11 . The semiconductor package of claim 1 , wherein the power bus is a first power bus, wherein the apparatus further comprises:
a fourth VR; and a second power bus, wherein the third VR is coupled between the first domain and the second power bus, and wherein the fourth VR is coupled between the second domain and the second power bus.

12 . The semiconductor package of claim 11 , wherein:
the third VR is to transmit power between the first domain and the second power bus; and the fourth VR is to transmit power between the second domain and the second power bus.

13 . The semiconductor package of claim 12 , further comprising:
a third domain comprising third one or more circuitries, wherein the third domain is to receive power from the second power bus.

14 . The semiconductor package of claim 1 , further comprising:
a fourth VR; and a third domain comprising third one or more circuitries, wherein the third VR is coupled between the first domain and the third domain, wherein the fourth VR is coupled between the second domain and the third domain, and wherein the third domain is to receive power from one or both of: the first domain via the third VR, or the second domain via the fourth VR.

15 . The semiconductor package of claim 1 , wherein the third VR is to receive power from the power bus via one or both the first or second domains, and wherein the third VR is to refrain from receiving power from the power bus by bypassing the first and second domains.

16 . A system comprising:
a memory to store instructions; a processor coupled to the memory, the processor to execute the instructions; a wireless interface to facilitate communication between the processor and another system; a first domain comprising one or more of the memory, the processor, or the wireless interface; a second domain comprising another one or more of the memory, the processor, or the wireless interface; a first voltage regulator (VR) to supply power to the first domain from a power bus; a second VR to supply power to the second domain from the power bus; and a third VR coupled between the first and second domains, the third VR to perform at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.

17 . The system of claim 16 , further comprising:
a substrate; and a first die and a second die stacked on the substrate, wherein the first VR comprises one or more inductors and one or more switches, wherein the first die comprises the first domain and the second domain, and wherein the second die comprises the one or more switches of the first VR.

18 . A method comprising:
supplying, by a first Direct Current (DC) to DC converter (DC-DC converter), power from a power bus to a first domain, the first domain comprising first one or more circuitries; supplying, by a second DC-DC converter, power from the power bus to a second domain, the second domain comprising second one or more circuitries; and transmitting, by a cross-domain DC-DC converter, power from or to at least one of the first or second domains.

19 . The method of claim 18 , wherein the cross-domain DC-DC converter is a first cross-domain DC-DC converter, and wherein the method further comprises:
transmitting, by a second cross-domain DC-DC converter, power between a common power bus and the second domain, wherein transmitting, by the first cross-domain DC-DC converter, power from or to at least one of the first or second domains comprises:
transmitting, by the first cross-domain DC-DC converter, power between the common power bus and the first domain.

20 . The method of claim 19 , further comprising:
transmitting, by a third cross-domain DC-DC converter, power between the common power bus and a third domain.

Assignees

• Intel Corp

Inventors

• Choi Beomseok
• Kulasekaran Siddharth
• Bharath Krishna

Classifications

• H10W90/00

  Package configurations · CPC title

• H02M3/1582

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• G05F1/465 Primary

  Internal voltage generators for integrated circuits, e.g. step down generators · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H01L25/18

  Electricity · mapped topic