Carbon nanotube ternary sram cell with improved stability and low standby power

Patent metadata

Field	Value
Publication number	US-2019341100-A1
Application number	US-201916403637-A
Country	US
Kind code	A1
Filing date	May 6, 2019
Priority date	May 7, 2018
Publication date	Nov 7, 2019
Grant date	—

Abstract

A carbon nanotube ternary SRAM cell with an improved stability and low standby power comprises a write bit line, a read bit line, a column select bit line, an inverted column select bit line, a write word line, an inverted write word line, a read word line, an inverted read word line, a first P-type CNFET, a second P-type CNFET, a third P-type CNFET, a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a ninth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh CNFET, an eighth N-type CNFET and a ninth N-type CNFET. The carbon nanotube ternary SRAM cell has the advantages of being lower in power consumption, capable of solving the half-select problem and the read-disturb problem and high in static noise margin.

First claim

What is claimed is:

1 . A carbon nanotube ternary SRAM cell with an improved stability and low standby power, comprising a write bit line, a read bit line, a column select bit line, an inverted column select bit line, a write word line, an inverted write word line, a read word line, an inverted read word line, a first P-type CNFET, a second P-type CNFET, a third P-type CNFET, a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a ninth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh CNFET, an eighth N-type CNFET and a ninth N-type CNFET,
wherein a power supply is accessed to a source of the first P-type CNFET, a source of the second P-type CNFET, a source of the third P-type CNFET and a source of the sixth P-type CNFET; a gate of the first P-type CNFET, a gate of the second P-type CNFET, a gate of the first N-type CNFET, a gate of the second N-type CNFET, a drain of the eighth N-type CNFET, a drain of the eighth P-type CNFET, a drain of the fourth P-type CNFET, a drain of the fifth P-type CNFET, a gate of the fifth P-type CNFET, a drain of the fourth N-type CNFET, a drain of the fifth N-type CNFET and the gate of the fifth N-type CNFET are connected; a drain of the first P-type CNFET, a drain of the first N-type CNFET, a gate of the third P-type CNFET, a gate of the fourth N-type CNFET and a gate of the sixth N-type CNFET are connected; a drain of the second P-type CNFET, a drain of the second N-type CNFET, a gate of the fourth P-type CNFET, a gate of the third N-type CNFET and a gate of the sixth P-type CNFET are connected; a drain of the third P-type CNFET, a source of the fourth P-type CNFET and a source of the fifth P-type CNFET are connected; a drain of the sixth P-type CNFET, a drain of the sixth N-type CNFET, a drain of the seventh P-type CNFET and a drain of the seventh N-type CNFET are connected; a gate of the seventh P-type CNFET is connected to the inverted read word line; a source of the seventh P-type CNFET and a source of the seventh N-type CNFET are connected to the read bit line; a gate of the eighth P-type CNFET is connected to the inverted column select bit line; a source of the eighth P-type CNFET, a source of the eighth N-type CNFET, a drain of the ninth P-type CNFET and a drain of the ninth N-type CNFET are connected; a gate of the ninth P-type CNFET P 9 is connected to the inverted write word line; a source of the ninth P-type CNFET and a source of the ninth N-type CNFET are connected to the write bit line; a source of the first N-type CNFET, a source of the second N-type CNFET, a source of the third N-type CNFET and a source of the sixth N-type CNFET are all grounded; a drain of the third N-type CNFET, a source of the fourth N-type CNFET and a source of the fifth N-type CNFET are connected; a gate of the seventh N-type CNFET is connected to the read word line; a gate of the eighth N-type CNFET is connected to the column select bit line; and a gate of the ninth N-type CNFET is connected to the write word line.

2 . The carbon nanotube ternary SRAM cell with an improved stability and low standby power according to claim 1 , wherein the first P-type CNFET has a chirality vector of (10, 0), the second P-type CNFET has a chirality vector of (19, 0), the third P-type CNFET has a chirality vector of (13, 0), the fourth P-type CNFET has a chirality vector of (13, 0), the fifth P-type CNFET has a chirality vector of (13, 0), the sixth P-type CNFET has a chirality vector of (13, 0), the seventh P-type CNFET has a chirality vector of (19, 0), the eighth P-type CNFET has a chirality vector of (19, 0), the ninth P-type CNFET has a chirality vector of (19, 0), the first N-type CNFET has a chirality vector of (28, 0), the second N-type CNFET has a chirality vector of (8, 0), the third N-type CNFET has a chirality vector of (13, 0), the fourth N-type CNFET has a chirality vector of (13, 0), the fifth N-type CNFET has a chirality vector of (13, 0), the sixth N-type CNFET has a chirality vector of (13, 0), the seventh N-type CNFET has a chirality vector of (19, 0), the eighth N-type CNFET has a chirality vector of (19, 0), and the ninth N-type CNFET has a chirality vector of (19, 0).

Assignees

• Univ Wenzhou

Inventors

• Li Gang
• Wang Pengjun
• Zhang Yuejun
• Chen Bo

Classifications

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title