Semiconductor packages having emi shielding layers

Patent metadata

Field	Value
Publication number	US-2019333865-A1
Application number	US-201816183538-A
Country	US
Kind code	A1
Filing date	Nov 7, 2018
Priority date	Apr 25, 2018
Publication date	Oct 31, 2019
Grant date	—

Abstract

A semiconductor package may include a chip disposed on a substrate, a conductive structure disposed on the substrate to include a conductive structure frame including a side surface facing at least one side surface of the chip and to include conductive structure fingers extending from the conductive structure frame toward an edge of the substrate, and an electromagnetic interference (EMI) shielding layer covering the chip and the conductive structure and contacting a side surface of an end of one or more of the conductive structure fingers.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a chip disposed on a substrate; a conductive structure disposed on the substrate to include a conductive structure frame including a side surface facing at least one side surface of the chip and to include conductive structure fingers extending from the conductive structure frame toward an edge of the substrate; and an electromagnetic interference (EMI) shielding layer covering the chip and the conductive structure and contacting a side surface of an end of one or more of the conductive structure fingers.

2 . The semiconductor package of claim 1 , wherein the substrate includes:
a substrate body; an upper solder resist layer disposed between the substrate body and the chip; and a lower solder resist layer disposed on a surface of the substrate body opposite to the chip.

3 . The semiconductor package of claim 2 ,
wherein the substrate further includes interconnection layers disposed in the substrate body; and wherein at least one of the interconnection layers is grounded and the grounded interconnection layer is connected to the conductive structure.

4 . The semiconductor package of claim 3 ,
wherein the grounded interconnection layer is disposed in the substrate body such that the grounded interconnection layer is not exposed at side surfaces of the substrate body; and wherein the EMI shielding layer is disposed to expose the side surfaces of the substrate body.

5 . The semiconductor package of claim 3 , wherein the grounded interconnection layer is exposed by an opening of the upper solder resist layer, the semiconductor package further comprising:
a bonding pad disposed in the opening of the upper solder resist layer to contact the grounded interconnection layer; and a wire connecting the conductive structure to the bonding pad.

6 . The semiconductor package of claim 3 , wherein the grounded interconnection layer is exposed by an opening of the upper solder resist layer, the semiconductor package further comprising:
a contact pad disposed in the opening of the upper solder resist layer to contact the grounded interconnection layer; and a conductive adhesive layer disposed between the conductive structure and the contact pad.

7 . The semiconductor package of claim 3 , wherein the grounded interconnection layer is exposed by an opening of the upper solder resist layer, the semiconductor package further comprising:
a conductive adhesive layer disposed in the opening of the upper solder resist layer to contact the grounded interconnection layer.

8 . The semiconductor package of claim 1 ,
wherein the conductive structure frame includes: a first conductive structure frame spaced apart from a side surface of the chip and extending in a first direction; and a second conductive structure frame spaced apart from another side surface of the chip and extending in the first direction, and wherein the conductive structure fingers include: a plurality of first conductive structure fingers extending from an outer side surface of the first conductive structure frame opposite to the chip; and a plurality of second conductive structure fingers extending from an outer side surface of the second conductive structure frame opposite to the chip.

9 . The semiconductor package of claim 8 , wherein side surfaces of both ends of the first conductive structure frame extending in the first direction and side surfaces of both ends of the second conductive structure frame extending in the first direction are in contact with the EMI shielding layer.

10 . The semiconductor package of claim 9 , further comprising:
a molding member disposed on the substrate to cover the chip and the conductive structure and to expose the one or more side surfaces of the ends of the conductive structure fingers, wherein the EMI shielding layer covers the molding member, and wherein the side surfaces of the both ends of the first conductive structure frame extending in the first direction and the side surfaces of the both ends of the second conductive structure frame extending in the first direction are exposed at side surfaces of the molding member and are in contact with the EMI shielding layer.

11 . The semiconductor package of claim 8 ,
wherein the plurality of first conductive structure fingers are disposed to be spaced apart from each other in the first direction; and wherein the plurality of second conductive structure fingers are disposed to be spaced apart from each other in the first direction.

12 . The semiconductor package of claim 8 , further comprising:
a molding member disposed on the substrate to cover the chip and the conductive structure and to expose the one or more side surfaces of the ends of the conductive structure fingers, wherein the EMI shielding layer covers the molding member, wherein the first conductive structure fingers and the molding member are alternately arrayed in the first direction and are in contact with the EMI shielding layer; and wherein the second conductive structure fingers and the molding member are alternately arrayed in the first direction and are in contact with the EMI shielding layer.

13 . The semiconductor package of claim 1 , wherein the conductive structure frame is spaced apart from all of side surfaces of the chip and is configured to have a closed loop shape to surround all of the side surfaces of the chip.

14 . The semiconductor package of claim 13 , further comprising:
a molding member disposed on the substrate to cover the chip and the conductive structure and to expose the one or more side surfaces of the ends of the conductive structure fingers, wherein the EMI shielding layer covers the molding member, and wherein the conductive structure frame is embedded in the molding member such that the conductive structure frame is not exposed at any surface of the molding member.

15 . The semiconductor package of claim 13 , wherein the conductive structure fingers are disposed to be spaced apart from each other along all side surfaces of the semiconductor package.

16 . The semiconductor package of claim 15 , further comprising:
a molding member disposed on the substrate to cover the chip and the conductive structure and to expose the one or more side surfaces of the ends of the conductive structure fingers, wherein the EMI shielding layer covers the molding member, and wherein the exposed side surfaces of the conductive structure fingers and the molding member are alternately arrayed along all the side surfaces of the semiconductor package and are in contact with the EMI shielding layer.

17 . The semiconductor package of claim 1 , further comprising interconnection layers disposed in the substrate,
wherein each of the interconnection layers includes a copper material, and wherein the conductive structure includes a stainless steel material.

18 . A semiconductor package comprising:
a substrate configured to include a substrate body having an interconnection layer connected to a ground terminal, an upper solder resist layer disposed on a top surface of the substrate body, and a lower solder resist layer disposed on a bottom surface of the substrate body; a chip disposed on the upper solder resist layer; a conductive structure disposed on the upper solder resist layer, wherein the conductive structure includes a first conductive structure frame that is spaced apart from a side surface of the chip and extends in a first direction, a second conductive structure frame that is spaced apart from another s

Assignees

• Sk Hynix Inc

Inventors

• Choi Bok Kyu
• Eom Juil
• Lim Sang Joon

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W72/354

  comprising polymers · CPC title