Fully aligned via in ground rule region

Patent metadata

Field	Value
Publication number	US-2019311948-A1
Application number	US-201916436117-A
Country	US
Kind code	A1
Filing date	Jun 10, 2019
Priority date	Sep 20, 2017
Publication date	Oct 10, 2019
Grant date	—

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

First claim

What is claimed:

1 . A method comprising:
depositing a first conductive material to fill vias of minimum feature dimensions resulting in wire structures; forming another wire structure with a larger width than the minimum feature dimensions; recessing the first conductive material for the wire structures; forming fully aligned vias with a selected one of the wire structures and the other wire structure with the larger width; and depositing conductive material in the fully aligned vias to be in electrical contact with the recessed first conductive material and conductive material of the wire structure with the larger width.

2 . The method of claim 1 , wherein the first conductive material is Ru which is removed isotopically from the non-minimum width wire structure.

3 . The method of claim 1 , wherein the other wire structure with the larger width is filled with second conductive material therein.

4 . The method of claim 3 , further comprising forming a barrier layer and a liner under the second conductive material.

5 . The method of claim 4 , further comprising forming a liner under the first conductive material in the vias of minimum feature dimensions and recessing the liner with the first conductive material.

6 . The method of claim 5 , further comprising forming a cap material on a top surface of recessed first conductive material and the other wiring structure and removing the cap material over the top surface of the other wiring structure and the selected one of the wiring structure prior to forming the fully aligned vias.

7 . The method of claim 1 , wherein the other wire structure with the larger width than the minimum feature dimensions is formed by etching a trench into a substrate and filling the trench with the first conductive material on sidewalls thereof, and filling remaining portions of the trench with a second conductive material over the first conductive material, followed by the recessing of the first conductive material in the trench and for the forming of the wiring structures.

8 . The method of claim 1 , further comprising:
lining the other wire structure with the first conductive material; filling the other wire structure with second conductive material therein; and recessing the first conductive material when recessing the first conductive material in the wire structures of minimum feature dimensions.

9 . A method comprising:
forming a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; forming at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; forming an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and forming an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer, wherein the etch stop layer is formed directly on the recessed conductive material of another selected minimum ground rule conductive structure and the opening exposes the recessed conductive material of the selected minimum ground rule conductive structure and partly exposes an upper surface of the conductive material of the least one conductive structure.

10 . The method of claim 9 , wherein the recessed conductive material is Ru or Co.

11 . The method of claim 9 , further comprising planarizing conductive material of at least one conductive structure to be planar with the dielectric material.

12 . The method of claim 9 , further comprising forming a recessed liner under the conductive material, wherein the upper conductive material is in electrical contact with the recessed liner and the conductive material.

13 . A method comprising:
forming a plurality of minimum ground rule structures each of which comprises a recessed conductive material and having a minimum insulator spacing therebetween; forming at least one wiring structure having a larger dimension than the plurality of minimum ground rule structures, the at least one wiring structure comprising a liner material and a conductive material which is different than the recessed conductive material; and forming an upper interconnect structure fully aligned with and in direct electrical contact with a selected minimum ground rule structure and the at least one wiring structure.

14 . The method of claim 13 , wherein the recessed conductive material is Ru or Co.

15 . The method of claim 13 , further comprising planarizing conductive material of the at least one wiring structure to be planar with a dielectric material which is for a same wiring level as the plurality of minimum ground rule structures.

Assignees

• Globalfoundries Inc

Inventors

• Licausi Nicholas V
• Zhang Xunyuan

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title