Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2019287902-A1
Application number	US-201815921368-A
Country	US
Kind code	A1
Filing date	Mar 14, 2018
Priority date	Mar 14, 2018
Publication date	Sep 19, 2019
Grant date	—

Abstract

A semiconductor device includes a substrate, a semiconductor fin, first and second source/drains, a gate electrode, and a gate contact. The semiconductor fin is disposed on the substrate. The first and second source/drains is disposed on the semiconductor fin. The gate electrode is across the semiconductor fin and exposes the first and second source/drains. The gate contact is disposed on the gate electrode and has an elliptical profile with a major axis extending along a lengthwise direction of the gate electrode when viewed from above the gate contact.

First claim

1 . A semiconductor device, comprising:
a semiconductor fin on a substrate and extending in a y-direction; first and second source/drains on the semiconductor fin; a gate electrode across the semiconductor fin, extending in a x-direction transverse to the v-direction, and exposing the first and second source/drains; and a gate contact on the gate electrode and having an elliptical profile with a major axis extending along the x-direction.

2 . The semiconductor device of claim 1 , wherein the gate contact overlaps the semiconductor fin.

3 . The semiconductor device of claim 1 , wherein a length of the gate contact along the x-direction of the gate electrode is greater than a length along a lengthwise direction of the semiconductor fin.

4 . The semiconductor device of claim 1 , wherein the major axis of the elliptical profile of the gate contact intersects with a lengthwise direction of the semiconductor fin.

5 . The semiconductor device of claim 1 , further comprising a barrier layer surrounding the gate contact.

6 . The semiconductor device of claim 5 , wherein the barrier layer comprises a high-k dielectric material.

7 . The semiconductor device of claim 5 , further comprising an interlayer dielectric (ILD) layer on the substrate, wherein the gate contact is embedded in the ILD layer, and a dielectric constant of the ILD layer is less than a dielectric constant of the barrier layer.

8 . The semiconductor device of claim 1 , further comprising first and second S/D contacts respectively overlapping the first and second source/drains, wherein the gate contact is between the first and second S/D contacts.

9 . The semiconductor device of claim 1 , further comprising:
a S/D contact overlapping one of the first and second source/drains; and a barrier layer surrounding the S/D contact.

10 . The semiconductor device of claim 9 , wherein the barrier layer comprises a high-k dielectric material.

11 . The semiconductor device of claim 1 , further comprising a conductive line electrically connected to the gate contact and overlapping the semiconductor fin.

12 . A semiconductor device, comprising:
a first semiconductor fin on a substrate; first and second source/drains on the first semiconductor fin; a gate electrode across the first semiconductor fin; a gate contact disposed on the gate electrode; and a barrier layer surrounding the gate contact and made of a high-k dielectric material.

13 . The semiconductor device of claim 12 , wherein the gate contact has an elliptical profile.

14 . The semiconductor device of claim 13 , wherein the elliptical profile of the gate contact extends along a lengthwise direction of the gate electrode when viewed from above the gate contact.

15 . The semiconductor device of claim 12 , wherein the high-k dielectric material comprises HfO 2 , Ta 2 O 5 , TiO 2 , ZrO 2 , Al 2 O 3 , Y 2 O 3 , or combinations thereof.

16 . The semiconductor device of claim 12 , wherein an entirety of the gate contact vertically overlaps the gate electrode.

17 . The semiconductor device of claim 12 , further comprising a second semiconductor fin on the substrate, wherein the gate electrode is across the first and second semiconductor fins, and a portion of the gate contact is between the first and second semiconductor fins.

18 - 20 . (canceled)

21 . A semiconductor device, comprising:
a semiconductor fin on a substrate; a first source/drain and a second source/drain on the semiconductor fin; a gate electrode across a channel region of the semiconductor fin between the first source/drain and the second source/drain; and a gate contact on the gate electrode having an elliptical profile when viewed from top and overlapping with the channel region of the semiconductor fin.

22 . The semiconductor device of claim 21 , further comprising first and second source/drain contacts that are directly above the first and second source/drains, wherein the gate contact is directly between the first and second source/drain contacts when viewed from top.

23 . The semiconductor device of claim 21 , further comprising a gate via that lands on the gate contact, wherein the gate via is directly between the first and second source/drains when viewed from top.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon-Jhy

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title