Gate contact with vertical isolation from source-drain

Patent metadata

Field	Value
Publication number	US-9614047-B2
Application number	US-201615153249-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	Jan 23, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

First claim

What is claimed is:

1. A semiconductor structure comprising:
gate spacers located on opposite sides of a gate structure on a semiconductor substrate, the gate structure having a height greater than a height of the gate spacers;
an interlevel dielectric (ILD) layer located above the semiconductor substrate;
an isolation liner located above the gate spacers, the isolation liner filling a space between a first conductive material of the gate structure and an exposed sidewall of the ILD layer; and
a gate contact comprises a second conductive material and electrically connected to the gate structure, the gate contact vertically contacting the first conductive material of the gate structure and the isolation liner, and wherein the gate contact further comprises a metal liner that underlies the second conductive material.

2. The semiconductor structure of claim 1 , wherein a top surface of the isolation liner is coplanar with a top surface of the first conductive material in the gate structure.

3. The semiconductor structure of claim 1 , wherein the isolation liner comprises a high-k dielectric material selected from the group consisting of hafnium oxides, lanthanum oxides, and zirconium oxide.

4. The semiconductor structure of claim 1 , wherein the gate spacers comprise silicon nitride, silicon carbon oxynitride, silicon boron oxynitride, or a low-k dielectric material.

5. The semiconductor structure of claim 1 , wherein the first conductive material comprises tungsten or aluminum.

6. The semiconductor structure of claim 1 , wherein the gate structure further comprises a gate dielectric and a work function metal present over the gate dielectric, wherein the first conductive material is present over the work function metal.

7. The semiconductor structure of claim 6 , wherein the first conductive material is T-shaped having a lower portion surrounded by the work functional metal and an upper portion vertically contacting topmost surfaces of the gate dielectric and the work function metal.

8. The semiconductor structure of claim 6 , wherein the gate dielectric comprises SiO 2 , HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , or a mixture thereof, and wherein the work function metal comprises Zr, W, Ta, Hf, Ti, Al, Ru, Pa, Ti3Al, ZrAl, TaC, TiC, or TaMgC.

9. The semiconductor structure of claim 1 , further comprising another ILD layer located over the ILD layer, wherein the gate contact is laterally surrounded by an upper portion of the ILD layer and the another 1 LD layer.

10. The semiconductor structure of claim 9 , wherein each of the ILD layer and the another ILD layer comprises silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, a silicon based low-k dielectric material, a flowable oxide, a porous dielectric material, or an organic dielectric material.

11. The semiconductor structure of claim 1 , further comprising source-drain regions present in the semiconductor substrate adjacent to the gate structure.

12. The semiconductor structure of claim 1 , wherein the second conductive material comprises tungsten, copper, aluminum, silver, gold, or an alloy thereof.

13. The semiconductor structure of claim 1 , wherein a bottommost surface of the metal liner vertically contacts a top surface of the first conductive material of the gate structure and a top surface of the isolation liner.

14. The semiconductor structure of claim 1 , wherein a portion of the metal liner is located vertically contacting a portion of a top surface of ILD layer.

15. The semiconductor structure of claim 1 , wherein the metal liner comprises a first vertical portion and a second vertical portion, the second vertical portion is located above the first vertical portion, and is laterally offset from the first vertical portion.

16. The semiconductor structure of claim 6 , wherein a sidewall of the isolation liner contacts a sidewall of the first conductive material and a sidewall of the gate dielectric.

17. The semiconductor structure of claim 11 , further comprising a source-drain contact located over the source-drain regions, wherein the first conductive material of the gate structure is electrically isolated from the source-drain contact by the isolation liner.

18. A semiconductor structure comprising:
gate spacers located on opposite sides of a gate structure on a semiconductor substrate, the gate structure having a height greater than a height of the gate spacers, and wherein the gate structure further comprises a gate dielectric and a work function metal present over the gate dielectric, wherein the first conductive material is present over the work function metal;
an interlevel dielectric (ILD) layer located above the semiconductor substrate;
an isolation liner located above the gate spacers, the isolation liner filling a space between a first conductive material of the gate structure and an exposed sidewall of the ILD layer, and wherein a sidewall of the isolation liner contacts a sidewall of the first conductive material and a sidewall of the gate dielectric; and
a gate contact electrically connected to the gate structure, the gate contact vertically contacting the first conductive material of the gate structure and the isolation liner.

Assignees

• IBM
• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Horak David V
• Ponoth Shom S
• Pranatharthiharan Balasubramanian
• Xie Ruilong

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/495

  Electricity · mapped topic