Electronic device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2019259779-A1
Application number	US-201916399227-A
Country	US
Kind code	A1
Filing date	Apr 30, 2019
Priority date	Dec 26, 2016
Publication date	Aug 22, 2019
Grant date	—

Abstract

An electronic device includes a plurality of layers formed on a silicon-on-insulator (SOI) substrate. The SOI substrate includes a support substrate, a buried insulating layer formed on the support substrate, and a silicon layer formed on the buried insulating layer. A membrane structure of the electronic device includes the plurality of layers, the buried insulating later and the silicon layer but does not include the support substrate. A passivation film covers an upper surface and a side surface of the membrane structure.

First claim

1 . An electronic device comprising:
a plurality of layers formed on a silicon-on-insulator (SOI) substrate, the SOI substrate including a support substrate, a buried insulating layer formed on the support substrate, and a silicon layer formed on the buried insulating layer; a membrane structure including the plurality of layers, the buried insulating layer and the silicon layer, but not including the support substrate; and a passivation film covering an upper surface and a side surface of the membrane structure.

2 . The electronic device according to claim 1 , wherein the passivation film is formed of a silicon nitride film.

3 . The electronic device according to claim 2 , wherein the passivation film comprises a silicon oxide film formed on the upper and side surfaces of the membrane structure and a silicon nitride film formed on the silicon oxide film.

4 . The electronic device according to claim 1 , wherein the passivation film comprises a silicon oxide film formed on the upper and side surfaces of the membrane structure and a silicon nitride film formed on the silicon oxide film.

5 . The electronic device according to claim 1 , wherein:
the electronic device includes the membrane structure and an adjacent structure containing the plurality of layers and the SOI substrate, the membrane structure and the adjacent structure being separated by a scribe line which extends through the plurality of layers to the buried insulating layer; and side surfaces of the plurality of layers located on opposite sides of the scribe line is covered with the passivation film.

6 . The electronic device according to claim 2 , wherein:
the electronic device includes the membrane structure and an adjacent structure containing the plurality of layers and the SOI substrate, the membrane structure and the adjacent structure being separated by a scribe line which extends through the plurality of layers to the buried insulating layer; and side surfaces of the plurality of layers located on opposite sides of the scribe line is covered with the passivation film.

7 . The electronic device according to claim 3 , wherein:
the electronic device includes the membrane structure and an adjacent structure containing the plurality of layers and the SOI substrate, the membrane structure and the adjacent structure being separated by a scribe line which extends through the plurality of layers to the buried insulating layer; and side surfaces of the plurality of layers located on opposite sides of the scribe line is covered with the passivation film.

8 . The electronic device according to claim 4 , wherein:
the electronic device includes the membrane structure and an adjacent structure containing the plurality of layers and the SOI substrate, the membrane structure and the adjacent structure being separated by a scribe line which extends through the plurality of layers to the buried insulating layer; and side surfaces of the plurality of layers located on opposite sides of the scribe line is covered with the passivation film.

9 . The electronic device according to claim 1 , wherein the passivation film has a protrusion of 5 μm or less on the side surface of the membrane structure.

10 . A method of manufacturing an electronic device, the method comprising:
forming a plurality of layers on a silicon-on-insulator (SOI) substrate which includes a support substrate, a buried insulating layer formed on the support substrate, and a silicon layer formed on the buried insulating layer; forming a membrane having an outer periphery by removing selected portions of at least some of the plurality of layers, the buried insulating layer and the silicon layer so as to expose the support substrate; and forming a passivation film covering both an upper surface and a side surface of the membrane structure.

11 . The method according to claim 10 , wherein the membrane structure includes the plurality of layers, the buried insulating layer and the silicon layer, but does not include the support substrate.

12 . The method according to claim 11 , wherein the passivation film is formed of a silicon nitride film.

13 . The method according to claim 10 , wherein the passivation film comprises a silicon oxide film formed on the upper and side surfaces of the membrane structure and a silicon nitride film formed on the silicon oxide film.

14 . The method according to claim 10 , wherein:
the outer periphery of the membrane structure faces and is spaced from an inner periphery of a portion of the electronic device, the inner periphery including the plurality of layers, the buried insulating layer and the silicon layer; and side surfaces of the outer periphery of the membrane structure and the inner periphery of the portion of the electronic device being covered with the passivation film.

15 . The method according to claim 1 , wherein the passivation film has a protrusion of 5 μm or less on the side surface of the membrane structure.

Assignees

• Murata Manufacturing Co

Inventors

• Izumitani Junko

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1908

  using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX] · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title