Bumped resonator structure
US-10263170-B1 · Apr 16, 2019 · US
Low loss architecture for superconducting qubit circuits
US2019237649A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2019237649-A1 |
| Application number | US-201916379824-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 10, 2019 |
| Priority date | Nov 30, 2017 |
| Publication date | Aug 1, 2019 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.
First claim
Opening claim text (preview).
What is claimed is: 1 . A structure comprising: a first surface comprising an inductive element of a resonator; and a second surface comprising a first portion of a capacitive element of the resonator and at least one qubit, wherein a second portion of the capacitive element of the resonator is on the first surface, wherein the first surface and the second surface comprise circuit planes, the circuit planes being on opposite sides of a substrate. 2 . The structure of claim 1 , wherein the capacitive element comprises an interconnect structure. 3 . The structure of claim 2 , wherein the interconnect structure comprises a through-silicon via. 4 . The structure of claim 1 , wherein an interconnect structure connecting the first and second portions forms an equipotential between the interconnect structure, the first portion, and the second portion. 5 . The structure of claim 1 , wherein the at least one qubit comprises a capacitive-type quantum bit. 6 . The structure of claim 1 , wherein the at least one qubit comprises an inductive-type quantum bit. 7 . The structure of claim 1 , wherein the resonator is a readout resonator. 8 . The structure of claim 7 , wherein the readout resonator is configured to read out a state of the at least one qubit. 9 . A structure comprising: a first surface comprising an inductive element of a resonator; and a second surface comprising a first portion of a capacitive element of the resonator and at least one qubit, wherein a second portion of the capacitive element of the resonator is on the first surface, wherein the first surface and the second surface comprise circuit planes, the circuit planes being on different substrates. 10 . The structure of claim 9 , wherein the capacitive element comprises an interconnect structure. 11 . The structure of claim 10 , wherein the interconnect structure comprises a solder bump. 12 . The structure of claim 9 , wherein an interconnect structure connecting the first and second portions forms an equipotential between the interconnect structure, the first portion, and the second portion. 13 . The structure of claim 9 , wherein the at least one qubit comprises a capacitive-type quantum bit. 14 . The structure of claim 9 , wherein the at least one qubit comprises an inductive-type quantum bit. 15 . The structure of claim 9 , wherein the resonator is a readout resonator configured to read out a state of the at least one qubit. 16 . A structure comprising: a first surface comprising an inductive element; a second surface comprising a first portion of a capacitive element and at least one qubit, wherein a second portion of the capacitive element is on the first surface; and an interconnect structure coupling the first and second portions to form an equipotential between the interconnect structure, the first portion, and the second portion. 17 . The structure of claim 16 , wherein a resonator comprises the inductive element and the capacitive element. 18 . The structure of claim 17 , wherein the resonator comprises the interconnect structure. 19 . The structure of claim 16 , wherein the interconnect structure comprises a solder bump. 20 . The structure of claim 16 , wherein the interconnect structure comprises a through-silicon via.
Assignees
Inventors
Classifications
Package configurations · CPC title
Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title
Multilayer dielectric · CPC title
Microstripline resonators (H01P7/088 takes precedence) · CPC title
Special shape resonators · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2019237649A1 cover?
- A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H01L39/223. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).