Fast boot systems and methods for programmable logic devices

Patent metadata

Field	Value
Publication number	US-2019205144-A1
Application number	US-201816228647-A
Country	US
Kind code	A1
Filing date	Dec 20, 2018
Priority date	Dec 29, 2017
Publication date	Jul 4, 2019
Grant date	—

Abstract

Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

First claim

1 . A method comprising:
receiving configuration data associated with a programmable logic device (PLD), wherein the PLD comprises an array of configuration memory cells comprising a plurality of logic block memory cells associated with a logic fabric of the PLD and a plurality of input/output (I/O) block memory cells associated with an I/O fabric of the PLD; programming a subset of the I/O block memory cells with a first portion of the configuration data; providing a first wakeup signal to wake up functionality associated with a portion of the I/O fabric associated with the subset of the I/O block memory cells; programming remaining configuration memory cells of the array with a second portion of the configuration data, wherein the remaining configuration memory cells comprise at least a subset of the logic block memory cells; and providing a second wakeup signal to wake up functionality associated with at least a portion of the logic fabric associated with the subset of the logic block memory cells.

2 . The method of claim 1 , further comprising:
in response to the first wakeup signal, transitioning the portion of the I/O fabric from a configuration mode to a fast boot operation mode, and in response to the second wakeup signal, transitioning the portion of the I/O fabric from the fast boot operation mode to a system operation mode and transitioning the portion of the logic fabric from the configuration mode to the system operation mode.

3 . The method of claim 2 , further comprising:
in response to the first wakeup signal, providing, by the portion of the I/O fabric, a first functionality; within a predetermined amount of time after transitioning into the system operation mode, maintaining, by the portion of the I/O fabric, the first functionality; and after the predetermined amount of time, providing, by the portion of the I/O fabric, a second functionality.

4 . The method of claim 1 , further comprising operating the portion of the I/O fabric while the programming the remaining configuration memory cells is performed.

5 . The method of claim 1 , wherein the subset of the logic block memory cells is a first subset of the logic block memory cells, wherein the portion of the logic fabric is a first portion of the logic fabric, the method further comprising:
programming a second subset of the logic block memory cells with a third portion of the configuration data, wherein the providing the first wakeup signal comprises providing the first wakeup signal to wake up functionality associated with a second portion of the logic fabric.

6 . The method of claim 5 , wherein:
the functionality associated with the portion of the I/O fabric is based on the functionality associated with the second portion of the logic fabric, the array of configuration memory cells is arranged in rows and columns, the subset of the I/O block memory cells comprises one or more sets of contiguous columns of the I/O block memory cells, and the second subset of the logic block memory cells comprises one or more sets of contiguous columns of the logic block memory cells that are contiguous with the one or more sets of contiguous columns of the I/O block memory cells.

7 . The method of claim 1 , wherein the configuration data comprises first authentication information associated with the subset of the I/O block memory cells, the method further comprising:
performing a first authentication associated with the first portion of the configuration data based on the first authentication information, wherein the providing the first wakeup signal, programming the remaining configuration memory cells, and providing the second wakeup signal are performed when the first authentication of the subset of the I/O block memory cells is successful.

8 . The method of claim 7 , wherein the performing the first authentication is performed after the programming the subset, wherein the configuration data comprises second authentication information associated with the remaining configuration memory cells, the method further comprising.
performing a second authentication associated with the second portion of the configuration data based on the second authentication information, wherein the providing the second wakeup signal is performed when the second authentication of the remaining configuration memory cells is successful.

9 . The method of claim 1 , wherein, after the programming the subset, each of the subset of the I/O block memory cells is associated with driving a 0, driving a 1, or being in tri-state.

10 . The method of claim 1 , wherein the subset of the I/O block memory cells comprises a first set of the I/O block memory cells and a second set of the I/O block memory cells, wherein the programming the subset of the I/O block memory cells comprises:
configuring an address shifter and a data shifter to program column-by-column; programming the first set of the I/O block memory cells column-by-column using the address shifter and data shifter; transitioning the address shifter and data shifter to program row-by-row; and after the transitioning, programming the second set of the I/O block memory cells row-by-row using the address shifter and data shifter.

11 . A programmable logic device (PLD) comprising:
an array of configuration memory cells comprising a plurality of logic block memory cells associated with a logic fabric of the PLD and a plurality of input/output (I/O) block memory cells associated with an I/O fabric of the PLD; a processing circuit configured to:
receive configuration data associated with the PLD;
program a subset of the I/O block memory cells with a first portion of the configuration data;
provide a first wakeup signal to wake up functionality associated with a portion of the I/O fabric associated with the subset of the I/O block memory cells;
program remaining configuration memory cells of the array with a second portion of the configuration data, wherein the remaining configuration memory cells comprise at least a subset of the logic block memory cells; and
provide a second wakeup signal to wake up functionality associated with at least a portion of the logic fabric associated with the subset of the logic block memory cells.

12 . The PLD of claim 11 , wherein the array is arranged in rows and columns, and wherein the plurality of I/O block memory cells is positioned around the plurality of logic block memory cells.

13 . The PLD of claim 11 , wherein the subset of the logic block memory cells is a first subset of the logic block memory cells, wherein the portion of the logic fabric is a first portion of the logic fabric, wherein the processing circuit is further configured to:
program a second subset of the logic block memory cells with a third portion of the configuration data, wherein the processing circuit is configured to provide the first wakeup signal to wake up functionality associated with a second portion of the logic fabric.

14 . The PLD of claim 11 , wherein:
the processing circuit comprises:
an address logic circuit configured to selectively assert rows or columns of the array;
a data write circuit configured to provide the configuration data to the array; and
a wakeup circuit configured to generate the first and second wakeup signals; and
the processing circuit is configured to program the array using the address logic circuit and the configuration data write circuit.

15 . The PLD of claim 11 , wherein:
the configuration data comprises authentication information associated with the subset, the processing circuit is further configured to perform an authentication o

Assignees

• Lattice Semiconductor Corp

Inventors

• Zhang Fulong
• Hands Gordon
• Singh Satwant
• Han Wei
• Lall Ravindar
• Coplen Joel
• Hegade Sreepada
• Ding Ming Hui

Classifications

• H03K19/17756 Primary

  for partial configuration or partial reconfiguration · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F21/575

  Secure boot · CPC title

• G06F2221/033

  Test or assess software · CPC title

• G06F3/0611

  in relation to response time · CPC title